Memory Subsystem Architect and Design Engineer

Amd

Confirmed live 2 days ago High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$232,000–$348,000 / yr
Posted
99 days ago
Freshness
Confirmed live 2 days ago
Closes
Jun 4, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k
This role $290k
$127k most similar roles pay here $372k

This role pays more than 95% of similar roles. Most pay $167,550–$231,000 — the shaded band above. At the midpoint, this role pays about $290k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

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View all roles at Amd

At a glance

TL;DR · Memory Subsystem Architect and Design Engineer

As a Memory Subsystem Architect and Design Engineer, you will join a dynamic team focused on advancing cutting-edge network technologies within an AI-driven roadmap. You will lead the architecture and bring up of hardware systems involving next-generation memory subsystems while collaborating with ASIC architects to evaluate memory controller IP and vendors. Your daily responsibilities include performing root cause analysis for legacy and next-gen memory issues, implementing corrective actions, and identifying opportunities for cost reductions and second sourcing. You will utilize tools such as Altium, Cadence, SPICE, and Python, while employing logic and protocol analyzers for hardware validation. The role requires deep expertise in DDR4 and DDR5 memory systems to solve complex technical challenges in network hardware design, ensuring robust PCB trace guidelines and high-performance system integration across the product lifecycle.

What you'll do

  • Lead the architecture and bring up of hardware systems involving next-generation memory subsystems.
  • Perform hands-on debug and root cause analysis to resolve complex memory issues.
  • Collaborate with ASIC architects to evaluate and select memory controller IP and vendors.
  • Partner with board designers to establish robust PCB trace design guidelines.
  • Work with silicon IP providers to optimize memory controller configurations.
  • Identify and implement hardware improvements, second sourcing options, and cost reductions.
  • Develop and execute test plans to validate hardware improvements.
  • Maintain technical documentation including design documents, user manuals, and technical notes.

What we're looking for

  • Preferred Master's degree in Electrical or Computer Engineering.
  • Extensive experience in hardware engineering with a focus on next-generation DDR5 and DDR4 memory systems.
  • Hands-on expertise in hardware troubleshooting, including component-level isolation, root cause analysis, repair, and rework.
  • Strong foundation in circuit design, PCB layout, and system integration.
  • Proficiency with CAD platforms like Altium or Cadence, simulation tools like SPICE, and scripting languages such as Python.
  • Proficiency in using memory test equipment, including logic and protocol analyzers.
  • Solid understanding of hardware validation, test methodologies, and failure analysis.
  • Excellent communication skills to collaborate across cross-functional teams and with external vendors.

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