below marketmost similar roles pay hereabove market
This role pays more than
94%
of similar roles. Most pay
$174,375–$227,500
— the blue band above.
At the midpoint, this role pays about
$255k
versus about
$201k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3497 open roles
on FindRole.
Listed pay typically runs
$174,149–$277,600
across 2702 roles with salary data.
JOB TITLE: Memory Packaging Engineer
The Memory Packaging Engineer joins the hardware team to architect memory solutions that power high-performance hardware. This role involves driving the definition, development, and qualification of next-generation memory packages throughout the entire product lifecycle. Key responsibilities include determining package architecture, guiding vendor roadmaps, and collaborating with cross-functional teams to solve electrical, mechanical, and thermal integration challenges. The engineer will define the plan of record for form factor, process, layout, stackup, and bill of materials while driving vendor failure analysis to improve yield. Required skills include expertise in thin-die stacking technologies like wirebond, flip-chip, and wafer bonding, as well as knowledge of packaging materials, SI/PI co-design, high-speed DDR signaling, and packaging inspection metrology to solve bandwidth and density scaling problems.
Determine next-generation package architecture by evaluating emerging packaging technologies.
Solve electrical, mechanical, and thermal integration challenges with cross-functional teams.
Drive vendor DOEs and failure analysis to improve downstream yield and reliability.
Define the memory package plan of record including form factor, process, layout, and BOM.
Manage memory vendors to develop materials and technologies for leading-edge design rules.
Guide memory partner roadmaps to enable bandwidth and density scaling.
Oversee the entire product lifecycle from initial concept through qualification.
What we're looking for
BS degree and 10+ years of relevant industry experience.
MS or PhD with 10+ years of industry experience in package design and assembly process development of high-bandwidth and high-density memory packages (preferred).
Strong knowledge of thin-die stacking technologies including wirebond, flip-chip, and wafer/die bonding (preferred).
Strong knowledge of packaging materials and design to engineer warpage and CTE properties and mitigate thermal challenges (preferred).
Solid working experience in package test and reliability, system-level downstream process interaction, and packaging inspection metrology (preferred).
Deep understanding of SI/PI co-design with memory die and high-speed DDR or differential signaling (preferred).
Understanding of how memory die floorplan and architecture influence package structure and routing (preferred).
Excellent communication skills for collaborating with internal teams and managing external vendors (preferred).
Semiconductor Packaging Design
SiP Packaging
Cadence APD
Allegro
Signal Integrity
Power Integrity
Design for Manufacturing
NPI
Package Layout
Si Floor Plan
Process & Technology Development
reliability, testing
BOM
HVM