Package Layout Engineer

Nvidia

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CANVORAZWACA
Salary: $108,000–$184,000 / yr
Employment: Full-time
Posted: 14 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $188k

This role $146k

$94k $239k

below market most similar roles pay here above market

This role pays less than 85% of similar roles. Most pay $161,875–$214,625 — the blue band above. At the midpoint, this role pays about $146k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Package Layout Engineer

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The Senior Package Layout Engineer joins the Layout team to collaborate with the Technical Package Lead and various design teams on the development of sophisticated IC substrate layouts for NVIDIA products. The role involves implementing high speed and density ASIC packages, performing substrate breakout patterns, and optimizing package pinouts while balancing system level trade-offs. Key responsibilities include performing package routing, placement, stack-up, and power distribution, as well as conducting design feasibility studies for size, cost, and performance. Candidates must utilize Cadence APD or SiP tool suites, Constraint Manager, and potentially Virtuoso, Calibre, or Valor. The position requires expertise in PCB layout for graphics cards or motherboards, HDI designs, and substrate layout for wire bond and flip chip packages while maintaining high-speed signal integrity practices.

Skills

Cadence APD PCB Layout Substrate Layout High-Speed Design Signal Integrity Virtuoso Calibre Valor Constraint Manager HDI Design IC Substrates Package Routing Stack-up Power Distribution CAD Library Databases

What you'll do

Implement high-speed and high-density ASIC packages.
Perform substrate breakout patterns for ASIC packages.
Optimize package pinout by incorporating system-level trade-offs of pin assignments.
Perform package routing, placement, stack-up, and power distribution using Cadence APD or SiP tools.
Conduct design feasibility studies to evaluate goals for size, cost, and system performance.
Develop symbols and CAD library databases using Cadence APD design tools.
Develop methodologies to improve layout productivity.

What we're looking for

Hold a B.S. in Electrical Engineering or equivalent experience.
Have 2+ years of experience in PCB Layout of graphics cards, motherboards, line cards, or related technology.
Have proven experience in substrate layout of wire bond and flip chip packages (preferred).
Have a significant background with Cadence APD or SiP and/or PCB layout tools including Constraint Manager.
Possess a solid understanding of high-speed design signal integrity practices.
Experience with HDI designs is a plus (preferred).
Experience with Virtuoso and Calibre is a plus (preferred).
Experience using Valor is helpful (preferred).