Integration RTL Design Engineer in San Jose, California | Advanced Micro Devices, Inc

Amd

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $166,400–$166,400 / yr
Posted: 77 days ago
Closes: Mar 26, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $185k

This role $166k

$149k most similar roles pay here $226k

This role pays less than 63% of similar roles. Most pay $159,266–$210,312 — the shaded band above. At the midpoint, this role pays about $166k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 71 open roles on FindRole.

Listed pay typically runs $178,400–$178,400 across 71 roles with salary data.

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At a glance

TL;DR · Integration RTL Design Engineer in San Jose, California | Advanced Micro Devices, Inc

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As a Senior ASIC Design Engineer at AMD’s Silicon Design team, you will lead the RTL design lifecycle for cutting-edge embedded products, from micro-architecture specification to production silicon. Your daily tasks include Verilog RTL coding, timing closure, and collaboration with physical design teams to ensure successful tape-outs. You will drive complex IP blocks through all phases of the ASIC development process, integrate them into SOC environments, and work closely with verification teams to maintain high-quality standards. Essential skills include expertise in Verilog RTL coding, comprehensive knowledge of the full ASIC design flow, proficiency in scripting languages like Python and Perl, and experience with industry-standard protocols such as AMBA AXI/AHB/APB. This role demands a seasoned professional with multiple production tape-outs under their belt and strong cross-functional collaboration abilities to deliver high-quality silicon solutions on schedule.

Skills

Verilog RTL PrimeTime Tempus SDC AMBA AXI AMBA AHB AMBA APB PCIe CXL Python Perl Tcl DFT DFD ARM architecture low-power design clock gating power gating voltage scaling formal verification AI-assisted design tools EDA technologies

What you'll do

Author detailed micro-architecture specifications and implement Verilog RTL for major IP blocks.
Drive design through all phases from specification to post-silicon validation.
Develop timing constraints and resolve static timing analysis violations.
Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity.
Implement DFT features and participate in RTL quality reviews.

What we're looking for

Proven track record with 2+ production ASIC tape-outs in senior design roles.
Expert-level Verilog RTL coding skills and deep understanding of synthesizable constructs.
Hands-on experience with the complete ASIC design flow from RTL to physical design.
Experience writing and debugging SDC timing constraints for complex designs.
Knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AHB/APB).
Proficiency in scripting languages like Python, Perl, Tcl for automation tasks.
Strong technical writing skills for design specifications and documentation.

Similar roles

ASIC/SoC Design Engineer, RTL design for SoC IPs in San Jose, California | Advanced Micro Devices, Inc

Amd

Santa Clara, CA 112 days ago $166,400–$166,400

Verilog RTL PrimeTime Tempus SDC AMBA AXI AMBA AHB AMBA APB PCIe CXL Python Perl Tcl Design-for-test Design-for-debug Physical Design Floor Planning Clock Tree Synthesis Power Grid Design

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