ASIC/SoC Design Engineer, RTL design for SoC IPs in San Jose, California | Advanced Micro Devices, Inc

Amd

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $166,400–$166,400 / yr
Posted: 112 days ago
Closes: Feb 26, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $192k

This role $166k

$152k most similar roles pay here $234k

This role pays less than 70% of similar roles. Most pay $165,200–$218,625 — the shaded band above. At the midpoint, this role pays about $166k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 71 open roles on FindRole.

Listed pay typically runs $178,400–$178,400 across 71 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · ASIC/SoC Design Engineer, RTL design for SoC IPs in San Jose, California | Advanced Micro Devices, Inc

Apply Now Log in to save

As a Senior ASIC Design Engineer at AMD's Silicon Design team, you will lead the RTL design lifecycle of cutting-edge IPs for next-generation embedded products, from micro-architecture specification to production silicon. Your daily tasks include Verilog RTL coding, timing closure, and physical design collaboration, ensuring compliance with PPA targets and industry-standard protocols like AMBA AXI/AHB/APB. You will drive full ASIC development through all phases, integrate complex IP blocks into SOC designs, and work closely with verification teams to ensure comprehensive functional coverage. Essential skills include expert Verilog RTL coding, experience with the complete ASIC design flow, and hands-on knowledge of SDC timing constraints. Preferred qualifications involve familiarity with PCIe or CXL protocols, scripting languages like Python or Perl, and mentoring junior engineers in a fast-paced environment.

Skills

Verilog RTL PrimeTime Tempus SDC AMBA AXI AMBA AHB AMBA APB PCIe CXL Python Perl Tcl Design-for-test Design-for-debug Physical Design Floor Planning Clock Tree Synthesis Power Grid Design

What you'll do

Author detailed micro-architecture specifications and implement Verilog RTL for major IP blocks.
Drive full ASIC development lifecycle from specification to post-silicon validation.
Develop timing constraints and resolve static timing analysis violations.
Integrate complex IP blocks into SOC environment ensuring proper connectivity and compliance with industry standards.
Implement design-for-test features and participate in RTL quality reviews.
Collaborate with physical design engineers on floor planning and clock tree synthesis.

What we're looking for

Proven track record with 2+ production ASIC tape-outs in senior roles.
Expert-level Verilog RTL coding skills and deep understanding of synthesizable constructs.
Hands-on experience across the full ASIC design flow from RTL to physical design.
Experience writing and debugging SDC timing constraints for complex designs.
Knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AHB/APB).
Strong ability to mentor junior engineers and lead design teams.

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX

Austin, TX 8 days ago

RTL2GDSII EDA tools CMOS digital design principles Standard cells DFT Scan MBIST LBIST Physical design flows

Save