Integrated Circuit Packaging Architect Engineer

Amd

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$162,800–$244,200 / yr
Posted
82 days ago
Freshness
Confirmed live yesterday
Closes
Aug 6, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $201k
This role $204k
$139k $255k
below market most similar roles pay here above market

This role pays more than 54% of similar roles. Most pay $166,875–$235,375 — the blue band above. At the midpoint, this role pays about $204k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Integrated Circuit Packaging Architect Engineer

The Integrated Circuit - Packaging Architect Engineer serves as a technology leader driving packaging architecture across client, server, gaming, and GPU products. This role involves collaborating with product design teams to define packaging roadmaps, including architecture, process definition, and Design for Manufacturing and Design for Yield guidelines. The engineer leads cross-functional teams to develop novel package architectures and processes from concept to qualification. Key responsibilities include driving test vehicle design, establishing yield roadmaps, and implementing data analytic tools. Required expertise includes semiconductor technology development, material science, thin film process development, and packaging. The candidate must possess leadership experience in architecture definition and yield improvement while communicating complex signals to technology partners and management to solve reliability and process development challenges within the semiconductor manufacturing environment.

What you'll do

  • Define package architectures and roadmaps with product architects during early definition stages.
  • Lead new package technology development initiatives from initial concept to full qualification.
  • Drive test vehicle design and manufacturing to establish design rules and DFM/DFY guidelines.
  • Establish a yield roadmap and lead the implementation of yield and data analytic tools.
  • Lead cross-functional teams across different geographies to design novel package architectures and processes.
  • Communicate technology development progress and technical problem-solving to executive leadership.
  • Engage with worldwide ecosystem partners to gather data and identify technical solutions.

What we're looking for

  • BS/MS/PhD in Material Science, Mechanical Engineering, Computer Science, Applied Mathematics, Electrical Engineering, or equivalent.
  • Proven track record of driving technology development in the semiconductor field.
  • Leadership experience driving engineering teams in architecture definition, process definition, and/or yield improvement.
  • Excellent oral and written communication skills to share complex signals and recommendations with partners and management.
  • Experience in semiconductor technology development (preferred).
  • Experience working with manufacturing partners such as suppliers, OSATs, and foundry partners (preferred).
  • In-depth knowledge in material science, thin film process development, and/or packaging (preferred).
  • Experience in a leadership role driving cross-functional teams (preferred).

More like this

Similar roles

Integrated Circuit Packaging Architect Engineer

Amd

San Jose, CA 82 days ago $209,600–$314,400
Semiconductor Technology Advanced Packaging DFM DFY Material Science Thin Film Process Development Yield Improvement Test Vehicle Design Process Definition Architecture Definition Manufacturing Foundry OSAT

IC Packaging Integration Engineer

Apple Inc

San Francisco, CA 95 days ago $184,700–$324,800
Semiconductor Packaging Design SiP Packaging Cadence APD Allegro Signal Integrity Power Integrity Design for Manufacturing NPI Package Layout Si Floor Plan Process & Technology Development reliability, testing BOM HVM
10+ yrs exp

Advanced Packaging Integration Engineer

Applied Materials

Santa Clara, CA 91 days ago $161,000–$221,000
Advanced Packaging Hybrid Bonding 2.5D/3D Heterogeneous Integration Semiconductor Processing TSV RDL Underfill Bumping Molding OSAT Processes Micro-LED CPO Design of Experiments SPC JMP MES Statistical Data Analysis Process Optimization

IC Packaging Integration Engineer

Apple Inc

Austin, TX 126 days ago
IC Packaging FOWLP 2.5D 3D MCM Signal Integrity Power Integrity Allegro AI ML Data Analytics DOE Failure Analysis NPI PCB Layout
10+ yrs exp

IC Packaging Integration Engineer

Apple Inc

Santa Clara, CA 160 days ago $184,700–$324,800
IC Packaging FOWLP 2.5D 3D MCM Signal Integrity Power Integrity Allegro DOE AI ML Data Analytics Failure Analysis NPI
10+ yrs exp

Senior IC Packaging Development Engineer

Nvidia

Santa Clara, CA 104 days ago
IC Packaging Failure Analysis NPI Flip-chip 2.5D/3D Packaging Wire Bonding Substrate Architecture Cadence Allegro Package Designer ANSYS ABAQUS SEM EDX CSAM X-Ray LIT Finite Element Modeling Material Characterization EDA Software
10+ yrs exp