IC Verification Engineer

Broadcom

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$143,800–$230,000 / yr
Employment
Full-time
Posted
14 days ago
Freshness
Confirmed live today
Closes
Apr 8, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $196k
This role $187k
$133k $240k
below market most similar roles pay here above market

This role pays less than 51% of similar roles. Most pay $168,500–$223,000 — the blue band above. At the midpoint, this role pays about $187k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · IC Verification Engineer

The IC Verification Engineer will join the team to architect and develop scalable, reusable testbench environments using established verification methodologies. The role involves driving test plans for Block, Core, and SOC features, writing functional coverage, and building pseudo-random tests to achieve full coverage and verification closure. Key responsibilities include debugging regression failures, analyzing coverage gaps, mentoring junior engineers, and leading documentation for verification strategies. The candidate must be proficient in SystemVerilog and methodologies such as UVM or VMM. Technical requirements include experience with complex protocols like PCI Express or AXI, along with scripting skills in Python or Perl and familiarity with Makefiles. This position focuses on the full ASIC cycle from architecture development to tapeout, ensuring high-quality verification of complex semiconductor designs.

What you'll do

  • Architect and develop scalable and reusable testbench environments using standard verification methodologies.
  • Drive test plans for all features across Block, Core, and SOC levels.
  • Write functional coverage for features and build pseudo-random tests to achieve full coverage.
  • Debug regression failures and analyze functional coverage gaps to improve test coverage.
  • Lead the documentation of verification strategies, including test plans and verification environments.
  • Lead reviews with design and architecture teams to ensure verification quality.
  • Mentor junior team members and guide their technical development.

What we're looking for

  • Bachelor's degree in Electrical/Electronics/Equivalent with 12+ years of experience.
  • Master's degree in Electrical/Electronics/Equivalent with 10+ years of experience.
  • 10+ years of experience in developing complex Verification Environments, Test plans, Functional coverage, and pseudo-random testing.
  • Experience completing a full ASIC cycle from Architecture development to Tapeout with a focus on Verification.
  • Proficiency in SystemVerilog and Verification Methodologies like UVM/VMM.
  • Good debug skills in analyzing regression failures and understanding complex designs.
  • Understanding of a complex protocol like PCI Express or other multi-layered protocols.
  • Experience in PCIe protocol (preferred); Scripting knowledge of Python or Perl (preferred); Comfort with Makefiles (preferred).

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