IC Verification Engineer

Broadcom

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Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $121,900–$195,000 / yr
Employment: Full-time
Posted: 14 days ago
Freshness: Confirmed live today
Closes: Apr 8, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $196k

This role $158k

$109k $238k

below market most similar roles pay here above market

This role pays less than 84% of similar roles. Most pay $168,500–$223,000 — the blue band above. At the midpoint, this role pays about $158k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · IC Verification Engineer

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The IC Verification Engineer will join the team to develop comprehensive test plans for Block, Core, and SOC features while writing functional coverage. The role involves architecting and developing scalable, reusable test benches using established verification methodologies. Daily responsibilities include building pseudo-random tests, debugging regression failures, and analyzing functional coverage gaps to improve test quality. The engineer must lead documentation for verification strategies and conduct reviews with design and architecture teams to drive efficiency. Key technical requirements include proficiency in SystemVerilog and verification methodologies such as UVM, VMM, or OVM. Candidates must demonstrate a strong command of Object-Oriented Programming principles and a deep understanding of complex multi-layered protocols, specifically PCIe. This role focuses on ensuring the functional integrity of semiconductor hardware components.

Skills

System Verilog UVM VMM OVM Object-Oriented Programming PCIe Functional Coverage Verification Methodology

What you'll do

Develop test plans and write functional coverage for Block, Core, and SOC features.
Architect and develop scalable, reusable test benches using standard verification methodologies.
Build pseudo-random tests to verify features and achieve full functional coverage.
Debug regression failures and analyze functional coverage gaps to improve test coverage.
Lead the documentation of verification strategies, including test plans and verification environments.
Lead verification reviews with design and architecture teams.
Drive continuous improvements in verification quality and efficiency.

What we're looking for

Bachelor's degree in Electrical Engineering or related field with 8+ years of relevant experience.
Master's degree in Electrical Engineering or related field with 6+ years of related experience.
6+ years of experience in writing and debugging complex test benches.
Deep understanding of verification aspects including testbench building, test plans, pseudo-random tests, and functional coverage.
Proficiency in SystemVerilog and verification methodologies like UVM, VMM, or OVM.
Exceptionally good command of Object-Oriented Programming principles.
Good understanding of a complex protocol like PCIe or other multi-layered protocols.
Knowledge of PCI Express protocol (preferred).

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