Hardware Design Engineer, Graphics Silicon Implementation

Qualcomm

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$161,800–$242,600 / yr
Posted
73 days ago
Freshness
Confirmed live yesterday
Closes
Dec 27, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $195k
This role $202k
$140k most similar roles pay here $254k

This role pays more than 54% of similar roles. Most pay $162,000–$227,350 — the shaded band above. At the midpoint, this role pays about $202k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Hardware Design Engineer, Graphics Silicon Implementation

The Hardware Design Engineer - Graphics Silicon Implementation joins the Adreno Graphics team to work on implementation and methodology for state-of-the-art GPU cores. This role involves managing various functions from RTL integration through physical design while collaborating with microarchitecture, physical design, and SoC teams. The engineer will be responsible for RTL integration, partitioning, transformation, and analysis, as well as ensuring implementation readiness through linting, custom checks, and clock domain crossing checks. Key responsibilities include delivering front-end design collateral, performing ECO methods for timing fixes, and managing power, performance, and area goals. Required technical skills include Verilog, SystemVerilog, and experience with Synopsys Design Compiler, Conformal LEC, Formality, and PrimeTime. Preferred competencies include UNIX, Perl, TCL, or shell scripting to optimize PPA, manage Power Intent, and perform static timing analysis for graphics silicon.

What you'll do

  • Integrate, implement, and develop state-of-the-art GPU cores for the Adreno Graphics team.
  • Perform RTL integration, partitioning, transformation, and analysis for ASIC design flows.
  • Ensure implementation readiness through RTL linting, custom checks, and clock domain crossing checks.
  • Package, qualify, and deliver front-end design collateral.
  • Develop innovative methods to improve the front-end design integration process.
  • Perform RTL synthesis using physically aware tools to manage power, performance, and area goals.
  • Execute formal verification for RTL-netlist and netlist-netlist checks using industry standard tools.
  • Implement ECO methods to resolve functional and timing issues during the design cycle.

What we're looking for

  • Bachelor's degree with 4+ years of experience, Master's with 3+ years, or PhD with 2+ years in a relevant engineering field.
  • Proficiency in Verilog and SystemVerilog for digital design and RTL development.
  • Knowledge of ASIC design flow including synthesis, static timing analysis, formal verification, and physical design.
  • Experience with Synopsys tools such as Design Compiler, Conformal LEC, Formality, and PrimeTime.
  • Ability to perform RTL integration, partitioning, transformation, and analysis.
  • Proficiency in scripting languages including UNIX, Perl, TCL, or shell scripting.
  • Knowledge of PPA optimization, Power Intent (UPF/CPF), CDC, RDC, and timing closure.
  • Experience with version control systems and managing design goals for power, performance, and area.

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