FPGA Prototyping Lead

Amd

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $200,000–$300,000 / yr
Posted: 99 days ago
Freshness: Confirmed live today
Closes: Jul 20, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k

This role $250k

$140k $317k

below market most similar roles pay here above market

This role pays more than 88% of similar roles. Most pay $160,000–$227,300 — the blue band above. At the midpoint, this role pays about $250k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · FPGA Prototyping Lead

Role Posting Log in to save

The FPGA Prototyping Lead joins the front-end design and integration team to drive FPGA prototyping strategy and execution for complex SoCs. This role involves defining architecture, methodology roadmaps, and platform strategies, including partitioning, interconnects, clocking, and debug infrastructure. The Lead will oversee RTL adaptation, implementation flows, verification infrastructure, and regression environments to enable early hardware validation and software bring-up. Key technical requirements include expertise in Synopsys HAPS, Cadence Protium, Vivado, and Vitis toolchains. The candidate must possess deep knowledge of high-speed interfaces like PCIe, DDR, Ethernet, USB, and HBM, alongside proficiency in SystemVerilog and Verilog. The work focuses on solving complex technical challenges in SoC prototyping, ensuring first-pass silicon success through rigorous timing closure, floorplanning, and performance optimization.

Skills

FPGA Prototyping SystemVerilog Verilog Vivado Vitis Synopsys HAPS Cadence Protium SoC Architecture PCIe DDR Ethernet AXI ACE CHI RTL Design Timing Closure CDC Analysis Floorplanning Hardware Validation Firmware

What you'll do

Define and own the FPGA prototyping architecture, methodology roadmap, and platform strategy for complex SoCs.
Lead the development and deployment of FPGA prototype platforms, including RTL adaptation and implementation flows.
Drive cross-functional collaboration to enable early hardware validation, software bring-up, and functional coverage goals.
Provide technical leadership to FPGA prototyping engineers through mentoring, design reviews, and project planning.
Establish engineering processes, documentation standards, and continuous improvement initiatives to improve scalability and quality.
Represent the FPGA prototyping organization in architecture reviews and customer-facing technical discussions.
Partner with EDA and FPGA tool vendors to drive technology adoption and resolve complex technical challenges.

What we're looking for

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
12+ years of experience in FPGA design, implementation, and SoC prototyping (preferred).
Proven experience leading FPGA prototyping efforts for large-scale semiconductor programs (preferred).
Hands-on experience with Synopsys HAPS and/or Cadence Protium platforms (preferred).
Strong knowledge of multi-FPGA partitioning, board bring-up, and high-speed interfaces such as PCIe, DDR, Ethernet, USB, and HBM (preferred).
Expert proficiency with AMD/Xilinx Vivado and Vitis toolchains (preferred).
Deep expertise in FPGA timing closure, floorplanning, CDC analysis, pipelining, and performance optimization (preferred).
Strong SystemVerilog and/or Verilog design and verification experience (preferred).

Similar roles

FPGA Design and Prototyping Engineer

Amd

San Jose, CA 33 days ago $166,400–$249,600

FPGA SystemVerilog Verilog Vivado Vitis SoC PCIe DDR Ethernet AXI ACE CHI HBM Synopsys HAPS Cadence Protium RTL Design Timing Closure CDC Analysis Floorplanning NoC

7+ yrs exp

Save

Senior FPGA Prototyping Engineer, Hardware

Nvidia

Santa Clara, CA 7 days ago $196,000–$310,500

FPGA Prototyping RTL Synthesis Place and Route Timing Closure Verilog System Verilog Synopsys Protocompiler Siemens VPS Xilinx Vivado VCS Verdi GDB Perl Shell Tcl LPDDR5 DDR5 CXL PCIe USB4 ChipScope Oscilloscope Logic Analyzer

10+ yrs exp

Save

Senior Solutions Engineer, FPGA/PCIe

Amd

San Jose, CA 47 days ago $200,000–$300,000

SystemVerilog Verilog ASIC FPGA RTL UVM Python Tcl Shell Scripting PCIe CXL AXI DDR5 Ethernet Vivado Palladium Protium Zebu Makefiles Hardware Debugging

Save

Senior Staff Design Verification Engineer

Amd

San Jose, CA 53 days ago $200,000–$300,000

Verilog SystemVerilog UVM DFT RTL Design Python Tcl Perl Shell Static Timing Analysis ASIC SoC FPGA Synopsys Cadence PCIe SerDes HBM Synthesis Place-and-Route

Save

Senior RTL Design Engineer

Amd

San Jose, CA 32 days ago $200,000–$300,000

Verilog SystemVerilog UVM DFT RTL Design Python Tcl Perl Shell Static Timing Analysis ASIC SoC FPGA Synopsys Cadence PCIe SerDes HBM Design Automation

Save

FPGA Design & Firmware Engineer, Staff

Qualcomm

San Diego, CA 11 days ago $145,600–$218,400

FPGA RTL SystemVerilog Verilog AMD/Xilinx Intel Vivado Quartus Python C++ PCIe AXI SerDes LVDS Embedded Linux ARM SpinalHDL RustHDL Git Timing Closure CDC

4+ yrs exp

Save