FPGA Engineer

Amazon Inc

Quick summary

Work type
On-site
Location
El Segundo, CANorthridge, CARedmond, WA
Salary
$136,000–$184,000 / yr
Posted
2 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $181k
This role $160k
$128k most similar roles pay here $215k

This role pays less than 74% of similar roles. Most pay $160,000–$202,675 — the shaded band above. At the midpoint, this role pays about $160k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 321 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 304 roles with salary data.

Most-posted roles

View all roles at Amazon Inc

At a glance

TL;DR · FPGA Engineer

Role Posting Log in to save

As an FPGA engineer on the Leo Government Solutions team at Amazon, you will contribute to Project Kuiper by creating and releasing FPGAs through various development phases, from architecture design to simulation validation. You will collaborate with RF and optical communications teams to define and implement digital logic functions in FPGA technology, using Verilog or SystemVerilog for RTL coding and Xilinx Vivado for implementation. Your responsibilities include writing testbenches, performing simulations, and debugging in a lab environment while working closely with system architects and firmware/software design teams to validate systems combining FPGA gateware and networking functions. This role requires proficiency in Linux scripting and familiarity with interface protocols like PCIe or DDR, as well as experience with formal verification techniques for optimizing cost, size, power, performance, and features.

Skills

Verilog SystemVerilog VHDL Xilinx Vivado Microchip Libero Linux Python Perl PCIe DDR FPGA RTL Simulation Timing Closure Debugging Vitis Formal Verification ARM DSP ISAs

What you'll do

  • Design and implement FPGA solutions for high-speed communication links.
  • Develop and validate digital logic functions in collaboration with system architects.
  • Perform simulation, timing closure, and debugging of RTL code in a lab environment.
  • Integrate new IP cores into existing designs using FPGA design tools like Vivado.
  • Conduct trade-off analysis to optimize technology resources for cost and performance.
  • Collaborate on bringing up and testing systems combining FPGA gateware with firmware.

What we're looking for

  • 5+ years of experience developing FPGA RTL code in System Verilog or VHDL.
  • Proficiency in Verilog, SystemVerilog, or VHDL and experience with Xilinx Vivado or Microchip Libero.
  • Strong debugging skills to identify bugs in architecture, algorithms, functionality, and performance.
  • Experience verifying logic at multiple levels from IP blocks to SoCs to full system testing.
  • Collaborative work experience with systems architects, hardware engineering design teams, and firmware/software design teams.

Related searches

More FPGA Engineer jobs FPGA Engineer jobs in El Segundo All jobs at Amazon Inc

More like this

Similar roles

FPGA Engineer

Amazon Inc

Redmond, WA 2 days ago $117,300–$160,000
Python System Verilog UVM Xilinx AMD FPGAs RTL coding CDC RDC AXI4 AXI Streaming CI/CD HDL simulation HIL testing FPGA optimization ASIC design
Save

Senior FPGA Engineer, Direct to Device

Amazon Inc

Redmond, WA 2 days ago $151,200–$204,600
Python C++ System Verilog Linux Unix Xilinx FPGAs AMD FPGAs AXI4 AXI Streaming High speed networking SerDes 50G/100G Ethernet Interlaken Phased array antennas RF systems FPGA optimization RTL coding Simulation Validation
Save

Senior FPGA Engineer, LEO Payload FPGA

Amazon Inc

Redmond, WA 2 days ago $159,200–$215,300
Verilog SystemVerilog Vivado Libero SoC ModelSim Python TCL PCIe DDR Ethernet Git UVM DO-254 Versal ACAP IGLOO2
Save

Lead ASIC Design Engineer

Amazon Inc

San Diego, CA +1 2 days ago $159,200–$215,300
RTL Verilog SystemVerilog VHDL SoC IP integration Ethernet SERDES LPDDR5/6X Arm CPU 3rd party IP blocks low power design DFT synthesis STA physical design deep sub-micron nodes communication systems wireless communications serial protocols SPI I2C I3C UART
Save

Senior FPGA Modem and Physical Layer Development Engineer

Amazon Inc

Austin, TX +3 2 days ago $159,200–$215,300
SystemVerilog VHDL Xilinx AMD_FPGA Intel_Altera_FPGA RF_front_end ARM_FPGA_SoC Physical_Layer_Design High_Speed_Signal_Generators Signal_Analyzers C C++ Low_Level_Drivers Hardware_In_The_Loop_Testing RTL_Development
Save

ASIC Design Verification Engineer

Amazon Inc

San Diego, CA +3 2 days ago $136,000–$184,000
UVM SystemVerilog C Matlab Python DPI-C SystemC Formal verification Verilog VCS DVflow CI/CD
Save