Senior FPGA Engineer, LEO Payload FPGA

Amazon Inc

Quick summary

Work type
On-site
Location
Redmond, WA
Salary
$159,200–$215,300 / yr
Posted
2 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $175k
This role $187k
$135k most similar roles pay here $224k

This role pays more than 73% of similar roles. Most pay $158,000–$192,942 — the shaded band above. At the midpoint, this role pays about $187k versus about $175k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 321 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 304 roles with salary data.

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At a glance

TL;DR · Senior FPGA Engineer, LEO Payload FPGA

Role Posting Log in to save

As a Senior FPGA Engineer at Amazon's LEO Payload team, you will collaborate with network communication system architects to design and implement digital logic functions in FPGAs for satellite communication systems. Your day-to-day responsibilities include developing complex FPGA architectures using Verilog HDL, leading Versal ACAP and IGLOO2 platform projects from concept through production, and creating comprehensive test benches and simulation environments. You will work closely with cross-functional teams to bring up and test integrated systems combining FPGA, firmware, RF, and networking functions. Essential skills include 7+ years of FPGA design experience, proficiency in Verilog HDL, and expertise with Xilinx Vivado and Microchip Libero SoC tools. This role involves high-speed interface protocols and a focus on resource-efficient designs for large-scale satellite communication systems.

Skills

Verilog SystemVerilog Vivado Libero SoC ModelSim Python TCL PCIe DDR Ethernet Git UVM DO-254 Versal ACAP IGLOO2

What you'll do

  • Design and develop complex FPGA architectures using Verilog HDL.
  • Lead FPGA design efforts for Versal ACAP and IGLOO2 platforms from concept to production.
  • Optimize RTL code for high-performance, resource-efficient designs.
  • Perform timing analysis, synthesis, place and route, and design verification.
  • Create comprehensive test benches and simulation environments for FPGA designs.

What we're looking for

  • 7+ years of FPGA design experience with Versal ACAP and IGLOO2 platforms.
  • Proficient in Verilog HDL for RTL design and verification.
  • Experience using Xilinx Vivado and Microchip Libero SoC tools.
  • Strong debugging skills and proficiency in simulation tools like ModelSim.
  • Knowledge of digital design principles, timing analysis, and clock domain crossing.
  • Collaborative work experience with cross-functional engineering teams.

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