Foundry Technology Engineer

Cisco

Confirmed live today High trust
Closes in 5 days Hybrid

Quick summary

Work type
Hybrid
Location
Holmdel, NJMaynard, MA
Salary
$154,900–$225,300 / yr
Employment
Full-time
Posted
2 days ago
Freshness
Confirmed live today
Closes
Oct 9, 2026 (soon)
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $183k
This role $190k
$136k most similar roles pay here $235k

This role pays more than 55% of similar roles. Most pay $149,375–$217,500 — the shaded band above. At the midpoint, this role pays about $190k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 240 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 187 roles with salary data.

Most-posted roles

View all roles at Cisco

At a glance

TL;DR · Foundry Technology Engineer

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The Foundry Technology Engineer joins the Component Quality and Technology team to drive the development and integration of next-generation Silicon Photonics and Electronic Integrated Circuits. This role serves as the technical interface between internal engineering teams and high-volume manufacturing foundries, managing the end-to-end PIC and EIC tape-out lifecycle from PDK engagement through process qualification. The engineer will develop and optimize photonic and electronic process flows across SiPh and CMOS platforms while executing critical modules focused on design-for-manufacturing principles. Key responsibilities include performing root-cause analysis, conducting Design of Experiments to address failure mechanisms, and managing wafer-scale processes using Wafer-to-Wafer or Die-to-Wafer methods. Required skills include proficiency in Cadence Virtuoso, Synopsys, and Klayout tools, alongside expertise in DFM, DFR, and DFT principles for the fabrication and characterization of integrated devices.

Skills

Silicon Photonics Electronic Integrated Circuits CMOS PDK DRC DFM DFR DFT Cadence Virtuoso Synopsys Klayout Wafer-to-Wafer Die-to-Wafer Hybrid Bonding Near-Package Optics Co-Packaged Optics DOE

What you'll do

  • Manage the end-to-end tape-out lifecycle for PIC and EIC components from PDK engagement to process qualification.
  • Serve as the primary technical interface between internal engineering teams and external high-volume manufacturing foundries.
  • Develop and optimize photonic and electronic process flows across SiPh and CMOS platforms.
  • Execute critical process modules using design-for-manufacturing (DFM) principles to ensure high yield during production ramp.
  • Lead wafer-scale processes for advanced EIC-PIC integration using Wafer-to-Wafer and Die-to-Wafer methods.
  • Perform root-cause analysis and Design of Experiments (DOE) to resolve failure mechanisms in integrated components.
  • Apply design-for-reliability (DFR) frameworks to identify and eliminate potential failure modes early in the development cycle.

What we're looking for

  • Minimum requirement of a PhD or MS in Electrical Engineering, Optics, Photonics, or a related field.
  • 4+ years of validated experience in chip development, foundry engagement, and process qualification in high-volume production environments.
  • Knowledge of DFM, DFR, and DFT principles for the fabrication, integration, and characterization of PIC and EIC devices.
  • Proficiency in IC design tools including Cadence Virtuoso, Synopsys, and Klayout.
  • Experience working with external foundries on process bring-up (preferred).
  • Hands-on experience with hybrid bonding and thin-wafer processing (preferred).
  • Familiarity or hands-on experience with near-package optics (NPO) or co-packaged optics (CPO) architectures (preferred).
  • Proven ability to lead projects within cross-functional, geographically distributed technical teams.

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