Formal Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Austin, TX
Posted: 61 days ago
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $167k

$121k most similar roles pay here $211k

This listing doesn't post a salary. Most similar roles pay $137,979–$196,937.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Formal Verification Engineer

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Join the leading Formal Verification team as a senior engineer and play a pivotal role in ensuring high-quality SoC design through comprehensive formal verification of critical components such as CPUs, GPUs, and security IP. Your daily tasks will include developing detailed test plans, proving design properties, identifying bugs, and collaborating with design teams to enhance micro-architectures. You’ll also craft innovative models to simulate security attacks and optimize verification processes using reusable code bases. Ideal candidates have extensive experience in VLSI validation, formal methods, and EDA tools, along with a strong background in scripting languages and temporal logic assertion-based languages like SVA or PSL. This role demands expertise in SoC design, a keen eye for detail, and the ability to tackle complex challenges head-on.

Skills

VLSI digital logic design formal methods SoC CPU GPU Cellular designs Temporal logic assertion-based languages SVA PSL EDA formal tools scripting language debugging skills CI/CD

What you'll do

Develop comprehensive formal verification test plans for design blocks and IP’s.
Prove properties of complex designs and identify potential security vulnerabilities.
Collaborate with design teams to enhance micro-architecture robustness.
Create novel models to simulate security attacks on hardware designs.
Implement reusable and optimized formal models and verification code.
Architect methodologies that ensure correctness in formal verification processes.

What we're looking for

At least 10 years of industry experience in silicon validation software engineering or related field.
Hands-on experience with VLSI and digital logic design and verification techniques.
Expertise in SoC, CPU, GPU, or Cellular designs.
Knowledge of formal methods and their application to hardware and systems.
Proficiency in temporal logic assertion-based languages like SVA or PSL.
Experience using EDA formal tools and developing custom tool solutions.

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