Formal Verification Engineer

Apple Inc

Quick summary

Work type
On-site
Location
Beaverton, OR
Posted
55 days ago

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Salary context

How this pay compares to similar roles

Similar $167k
$121k most similar roles pay here $211k

This listing doesn't post a salary. Most similar roles pay $137,979–$196,937.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Formal Verification Engineer

Join the world-class Formal Verification team as a mid-level Silicon Validation Engineer, where you will play a crucial role in the System-on-a-chip (SoC) design verification process. Your daily responsibilities include collaborating with designers to develop and implement comprehensive validation strategies using state-of-the-art tools and methodologies. You will build robust testbenches and write efficient scripts to verify complex hardware designs, ensuring high-quality silicon products. Proficiency in languages such as SystemVerilog, UVM, and Python is essential, along with experience in formal verification tools like Cadence JasperGold or Synopsys Formality. This role offers a unique opportunity to work on large-scale projects that tackle intricate business challenges within the semiconductor industry.

What you'll do

  • Conduct formal verification on System-on-a-chip (SoC) designs.
  • Develop and maintain verification environments for SoC design validation.
  • Collaborate with design teams to ensure comprehensive coverage of verification tasks.
  • Analyze and debug complex hardware issues using advanced verification techniques.
  • Stay updated with the latest trends in silicon validation software engineering.

What we're looking for

  • Bachelor’s degree and at least 3 years of relevant industry experience.
  • Experience in silicon validation software engineering.
  • Strong background in hardware verification and SoC design collaboration.
  • Proficiency in formal verification methodologies and tools.
  • Collaborative work ethic with cross-functional teams.

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