Formal Verification Engineer

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: Beaverton, OR
Posted: 148 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Similar $187k

$126k most similar roles pay here $230k

This listing doesn't post a salary. Most similar roles pay $159,937–$214,000.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

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At a glance

TL;DR · Formal Verification Engineer

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As a Formal Verification Engineer within the Silicon Technologies group, you will perform complete formal verification for various design blocks and IPs including CPU, Cellular, Connectivity, Audio, Image Processing, Neural Networks, Memory/DMA Controllers, Security IP, Interconnects, and Power management subsystems. You will collaborate with design engineers to develop micro-architecture specifications, create comprehensive test plans featuring unique security requirements, and prove properties of the design to identify bugs. Your daily work involves crafting novel solutions for modeling security attacks, building reusable formal models, and architecting correct-by-construction methodologies. The role requires expertise in VLSI, digital logic design, and formal methods applied to hardware. You will utilize temporal logic assertion-based languages like SVA or PSL, employ EDA formal tools, and use scripting languages to ensure the robustness of complex system-on-a-chip micro-architectures.

Skills

Formal Verification SVA PSL VLSI Digital Logic Design SoC CPU GPU Memory Consistency Cache Coherence Micro-architecture Hardware Specification System-on-a-Chip instruction-set architecture

What you'll do

Develop formal micro-architecture specifications with security enclave design engineers.
Create comprehensive formal verification test plans including unique security requirement verifications.
Prove design properties and identify bugs to improve micro-architecture with design teams.
Model security attacks and prove the robustness of complex design micro-architectures.
Develop and implement reusable, optimized formal models and verification codebases.
Architect correct-by-construction design methodologies to improve verification efficiency and productivity.

What we're looking for

A bachelor's degree is required.
At least 3 years of relevant industry experience in silicon validation software engineering or a related field is required.
Experience with VLSI and digital logic design and verification techniques or formal methods is preferred.
Knowledge of Formal Method or Formal Verification technologies is preferred.
Proficiency in temporal logic assertion-based languages such as SVA or PSL is preferred.
Experience using EDA formal tools and tool development experience is preferred.
Proficiency in any scripting language with excellent debugging skills is required.
Exposure to CPU instruction-set architectures, memory consistency, or cache coherence principles is preferred.

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