Formal Verification Engineer

Apple Inc

Confirmed live 2 days ago Low trust

Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$184,700–$324,800 / yr
Posted
154 days ago
Freshness
Confirmed live 2 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $189k
This role $255k
$115k most similar roles pay here $347k

This role pays more than 96% of similar roles. Most pay $162,750–$214,500 — the shaded band above. At the midpoint, this role pays about $255k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Formal Verification Engineer

As a Formal Verification Engineer within the Silicon Technologies group, you will join a team focused on the design and manufacture of high-performance, power-efficient system-on-a-chip (SoC) architectures. You will be responsible for performing complete formal verification for various design blocks and IPs, including CPU, memory controllers, security IP, and interconnects. Your daily work involves developing micro-architecture specifications, creating comprehensive test plans with unique security requirements, proving properties of the design, and finding bugs to improve micro-architecture. You will build reusable models, architect correct-by-construction methodologies, and model security attacks. The role requires expertise in VLSI, digital logic design, and formal methods. Key technical skills include proficiency in temporal logic assertion-based languages like SVA or PSL, experience with EDA formal tools, scripting for debugging, and knowledge of CPU instruction-set architectures and memory consistency principles.

What you'll do

  • Develop formal micro-architecture specifications with Security Enclave design engineers.
  • Create comprehensive formal verification test plans that include unique security requirements.
  • Prove design properties and identify bugs to improve micro-architecture designs.
  • Model security attacks and prove the robustness of complex design architectures.
  • Develop and implement reusable, optimized formal models and verification codebases.
  • Architect correct-by-construction design methodologies to improve verification efficiency and productivity.

What we're looking for

  • A minimum of a BS degree is required.
  • Minimum of 10 years of relevant industry experience in silicon validation software engineering or a related field.
  • Experience with VLSI and digital logic design and verification techniques.
  • Knowledge of formal methods and their application to hardware, software, or systems.
  • Proficiency in temporal logic assertion-based languages such as SVA or PSL.
  • Experience using EDA formal tools and tool development experience.
  • Proficiency in any scripting language with excellent debugging skills.
  • Exposure to CPU instruction-set architectures, memory consistency, or cache coherence principles.

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