Formal Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $181,100–$318,400 / yr
Posted: 61 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $166k

This role $250k

$107k most similar roles pay here $341k

This role pays more than 95% of similar roles. Most pay $137,979–$193,937 — the shaded band above. At the midpoint, this role pays about $250k versus about $166k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Formal Verification Engineer

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Join the leading Formal Verification team as a senior engineer, contributing to cutting-edge System-on-a-chip (SoC) design verification efforts. You will collaborate closely with design teams to ensure robust and efficient chip validation, leveraging advanced formal methods to verify complex hardware designs. Your daily tasks include developing and maintaining verification environments using industry-standard tools and languages such as SVA (SystemVerilog Assertions), Python, and Perl. Ideal candidates possess extensive experience in silicon validation software engineering, with a strong background in formal verification techniques and scripting for automation. This role offers the opportunity to work on large-scale projects that impact the future of semiconductor technology.

Skills

Formal Verification System-on-a-chip SoC design verification Python C++ Perl Shell scripting Unix/Linux CI/CD Git Jenkins Docker Kubernetes AWS Google Cloud Platform Azure PostgreSQL MySQL MongoDB JSON YAML

What you'll do

Develop and execute formal verification strategies for complex SoC designs.
Identify and mitigate critical design flaws through rigorous formal analysis techniques.
Collaborate with cross-functional teams to ensure comprehensive coverage of verification requirements.
Maintain up-to-date knowledge of industry trends in silicon validation and formal methods.
Document verification processes, results, and methodologies for future reference and training.

What we're looking for

At least 10 years of industry experience in silicon validation software engineering.
Minimum BS degree in a related technical field.
Proven track record working on System-on-a-chip (SoC) design verification.
Experience collaborating with cross-functional teams in hardware design.
Strong background in formal verification methodologies and tools.

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