Formal Verification Engineer

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$150,400–$277,600 / yr
Posted
148 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $189k
This role $214k
$119k most similar roles pay here $295k

This role pays more than 75% of similar roles. Most pay $161,500–$216,062 — the shaded band above. At the midpoint, this role pays about $214k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Formal Verification Engineer

As a Formal Verification Engineer within the Silicon Technologies group, you will perform complete formal verification for various design blocks and IPs, including CPU, Cellular, Connectivity, Audio, Image Processing, Neural Networks, Memory/DMA Controllers, Security IP, Interconnects, and Power management subsystems. You will collaborate with design engineers to develop micro-architecture specifications, create comprehensive test plans involving unique security requirements, and prove properties of the design to identify bugs. Your daily work involves crafting creative solutions for modeling security attacks, building reusable formal models, and architecting correct-by-construction methodologies. The role requires expertise in VLSI, digital logic design, and formal methods. You will utilize temporal logic assertion-based languages like SVA or PSL, employ EDA formal tools, and use various scripting languages to ensure the robustness of complex System-on-a-Chip micro-architectures while addressing memory consistency and cache coherence principles.

What you'll do

  • Develop formal micro-architecture specifications with security enclave design engineers.
  • Create comprehensive formal verification test plans that include unique security requirements.
  • Prove design properties and identify bugs to improve micro-architecture with design teams.
  • Model security attacks and prove the robustness of complex design architectures.
  • Develop and implement reusable, optimized formal models and verification codebases.
  • Architect correct-by-construction design methodologies to improve verification efficiency and productivity.

What we're looking for

  • A bachelor's degree is required.
  • Minimum of 3 years of relevant industry experience in silicon validation software engineering or a related field.
  • Experience with VLSI and digital logic design and verification techniques or formal methods.
  • Knowledge of formal method or formal verification technologies.
  • Proficiency in scripting languages with excellent debugging skills.
  • Experience with temporal logic assertion-based languages such as SVA or PSL.
  • Experience using EDA formal tools and tool development experience is a plus.
  • Exposure to CPU instruction-set architectures, memory consistency, or cache coherence principles.

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