Formal Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $147,400–$272,100 / yr
Posted: 57 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $166k

This role $210k

$112k most similar roles pay here $289k

This role pays more than 86% of similar roles. Most pay $137,979–$193,937 — the shaded band above. At the midpoint, this role pays about $210k versus about $166k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Formal Verification Engineer

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Join Apple's elite Formal Verification team as a senior engineer responsible for the complete formal verification of single or multiple design blocks and IPs in System-on-a-chip (SoC) projects. You will collaborate closely with design engineers to develop micro-architecture specifications, create comprehensive test plans, prove design properties, and enhance robustness against security attacks. Your daily tasks include crafting innovative solutions, developing reusable models, and optimizing verification code bases while improving formal verification methodologies for efficiency. Ideal candidates have hands-on experience in VLSI and digital logic design, expertise with EDA tools like SVA or PSL, proficiency in scripting languages, and a passion for advancing formal verification techniques in complex SoC designs.

Skills

VLSI digital logic design formal methods SoC CPU GPU Cellular designs Temporal logic assertion-based languages SVA PSL EDA formal tools scripting language debugging skills CI/CD

What you'll do

Develop comprehensive formal verification test plans for design blocks and IP’s.
Prove properties of complex designs and identify potential security vulnerabilities.
Collaborate with design teams to enhance micro-architecture robustness.
Create novel models to simulate security attacks on hardware designs.
Implement reusable and optimized formal verification code and models.
Architect methodologies that ensure correctness in formal verification processes.

What we're looking for

Minimum 3 years of relevant industry experience in silicon validation software engineering.
Hands-on experience with VLSI and digital logic design and verification techniques.
Knowledge of Formal Method technologies and application to hardware or systems.
Experience interpreting hardware specifications and using temporal logic assertion languages.
Proficiency in scripting languages and debugging skills.
Excellent interpersonal skills for collaboration with design teams.

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