Formal Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Beaverton, OR
Posted: 61 days ago
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $167k

$121k most similar roles pay here $211k

This listing doesn't post a salary. Most similar roles pay $137,979–$196,937.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Formal Verification Engineer

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Join the leading Formal Verification team as a senior engineer, playing a pivotal role in the design verification of complex System-on-a-chip (SoC) projects. You will collaborate closely with design engineers to ensure comprehensive coverage and robustness in silicon validation software engineering. Your daily tasks include developing and implementing formal verification methodologies, automating test cases, and conducting rigorous analysis to identify potential flaws before production. Proficiency in languages such as SystemVerilog, Python, and Perl is essential, along with expertise in formal verification tools like Cadence JasperGold or Synopsys Formality. This role demands a deep understanding of hardware design principles and the ability to work effectively within large-scale engineering teams tackling intricate business challenges in semiconductor technology.

Skills

Formal Verification System-on-a-chip (SoC) Python CI/CD Git Linux C++ Verilog UVM Perl Shell_scripting Docker Jenkins

What you'll do

Develop and maintain formal verification methodologies for complex SoC designs.
Create comprehensive test plans to ensure thorough coverage of design specifications.
Implement and optimize verification environments using advanced verification languages.
Analyze and debug formal verification results to identify and resolve issues efficiently.
Collaborate with cross-functional teams to integrate verification solutions into the design flow.

What we're looking for

At least 10 years of industry experience in silicon validation software engineering.
Bachelor’s degree in a related technical field required.
Experience working on System-on-a-chip (SoC) design verification.
Collaboration skills with design teams and formal verification experts.
Expertise in formal verification methodologies and tools.

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