Formal Verification Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$150,400–$277,600 / yr
Posted
21 days ago
Freshness
Confirmed live today

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $208k
This role $214k
$135k most similar roles pay here $293k

This role pays more than 65% of similar roles. Most pay $177,200–$239,462 — the shaded band above. At the midpoint, this role pays about $214k versus about $208k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3518 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2727 roles with salary data.

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At a glance

TL;DR · Formal Verification Engineer

As a Formal Verification Engineer within the Silicon Technologies group, you will perform complete formal verification for single or multiple design blocks and IPs, including CPU, Cellular, Connectivity, Audio, Image Processing, Neural Networks, Memory/DMA Controllers, Security IP, Power management subsystems, and Interconnects. You will collaborate with design engineers to develop micro-architecture specifications, create comprehensive test plans featuring unique security requirements, and prove properties of the design to identify bugs. Your daily work involves crafting novel solutions for modeling security attacks, building reusable formal models, and architecting correct-by-construction methodologies to improve verification efficiency. The role requires proficiency in scripting languages, experience interpreting hardware specifications, and knowledge of Formal Method or Formal Verification technologies. You will solve complex technical challenges related to the design and verification of high-performance, power-efficient system-on-a-chip architectures.

What you'll do

  • Develop formal micro-architecture specifications with Security Enclave design engineers.
  • Create comprehensive formal verification test plans that include unique security requirements.
  • Prove design properties and identify bugs to improve micro-architecture with design teams.
  • Model security attacks and prove the robustness of complex design micro-architectures.
  • Develop and implement reusable, optimized formal models and a verification code base.
  • Architect correct-by-construction design methodologies to improve formal verification efficiency and productivity.

What we're looking for

  • A bachelor's degree is required.
  • Minimum of 3 years of relevant industry experience in silicon validation software engineering or a related field.
  • Knowledge of Formal Method or Formal Verification technologies (preferred).
  • Experience interpreting hardware specifications (preferred).
  • Proficiency in any scripting language with excellent debugging skills (preferred).
  • Interest in learning and becoming an expert in SoC, CPU, GPU, or Cellular design (preferred).
  • Detail-oriented approach and passion for developing innovative formal verification solutions (preferred).
  • Excellent interpersonal skills (preferred).

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