Formal Verification Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$115,773–$194,700 / yr
Posted
21 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $208k
This role $155k
$101k most similar roles pay here $254k

This role pays less than 89% of similar roles. Most pay $177,200–$239,462 — the shaded band above. At the midpoint, this role pays about $155k versus about $208k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3518 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2727 roles with salary data.

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At a glance

TL;DR · Formal Verification Engineer

Formal Verification Engineer will join the Silicon Technologies group to perform complete formal verification for single or multiple design blocks and IPs, including CPU, Cellular, Connectivity, Audio, Image Processing, Neural Networks, Memory/DMA Controller, Security, Peripheral IP, Interconnects, and Power management subsystems. The role involves collaborating with Security Enclave design engineers to develop micro-architecture specifications, creating comprehensive test plans with unique security requirements, proving properties, finding bugs, and improving micro-architectures. Responsibilities include crafting solutions for modeling security attacks, developing reusable formal models, and architecting correct-by-construction methodologies. Required skills include a degree in electrical or computer engineering, proficiency in scripting languages, and debugging skills. Preferred qualifications include knowledge of Formal Method or Formal Verification technologies and experience interpreting hardware specifications to ensure high-quality functional products within the System-on-a-chip design space.

What you'll do

  • Develop formal micro-architecture specifications with security enclave design engineers.
  • Create comprehensive formal verification test plans including unique security requirements.
  • Prove design properties and identify bugs to improve micro-architecture.
  • Model security attacks and prove the robustness of complex designs.
  • Develop and implement reusable, optimized formal models and verification codebases.
  • Architect correct-by-construction design methodologies to improve verification efficiency.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or a related field.
  • Knowledge of Formal Method or Formal Verification technologies (preferred).
  • Experience interpreting hardware specifications (preferred).
  • Proficiency in any scripting language with excellent debugging skills (preferred).
  • Interest in learning and becoming an expert in SoC, CPU, GPU, or Cellular design (preferred).
  • Passionate about developing world-class/innovative formal verification solutions (preferred).
  • Detail oriented approach and desire to overcome challenges.
  • Excellent interpersonal skills.

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