Formal Verification Architect

Amd

Confirmed live 2 days ago High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$200,000–$300,000 / yr
Posted
32 days ago
Freshness
Confirmed live 2 days ago
Closes
Aug 10, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k
This role $250k
$126k most similar roles pay here $319k

This role pays more than 85% of similar roles. Most pay $175,000–$222,250 — the shaded band above. At the midpoint, this role pays about $250k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

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At a glance

TL;DR · Formal Verification Architect

Formal Verification Architect The Formal Verification Architect joins the NBIO organization's IOHUB team to develop advanced I/O connectivity, virtualization, and infrastructure technologies for data center, AI/ML, client, graphics, embedded, and semi-custom products. In this role, you will lead a team of engineers to define formal verification strategies, develop methodologies, and manage infrastructure architecture for complex IP and SoC designs. Daily responsibilities include creating test plans, performing deadlock/livelock analysis, and executing protocol verification for arbitration-intensive designs using advanced techniques like abstraction and decomposition. You will utilize tools such as JasperGold and VC-formal while working with SystemVerilog, Verilog, or VHDL. The role focuses on solving complex design challenges in the domain of high-performance interconnects and memory controllers by ensuring functional correctness through formal connectivity verification and bridging formal flows with UVM-based simulation environments to achieve silicon sign-off.

What you'll do

  • Lead and mentor a team of formal verification engineers across multiple IP and SoC projects.
  • Define formal verification architecture, methodologies, and development plans in partnership with design teams.
  • Develop comprehensive formal verification test plans and execute verification closure strategies.
  • Architect and maintain reusable formal verification environments, properties, and infrastructure.
  • Perform connectivity verification, deadlock/livelock analysis, and protocol verification for complex I/O designs.
  • Apply advanced techniques like abstraction, decomposition, and assume-guarantee to solve complex verification problems.
  • Debug and triage failures identified by formal tools to root-cause complex design issues.
  • Contribute to verification sign-off activities to ensure the delivery of high-quality silicon solutions.

What we're looking for

  • BS/MS degree in Engineering (Electrical, Electronics, Computer) or Computer Science.
  • Proven leadership experience guiding technical teams and mentoring engineers.
  • Expertise in formal verification methodologies including Static, Dynamic, FPV, and DPV.
  • Proficiency with JasperGold CDC/RDC and Connectivity apps is strongly preferred.
  • Experience with sequential/logical equivalence checking (SEC/LEC).
  • Ability to apply advanced techniques like abstraction, decomposition, and assume-guarantee reasoning.
  • Knowledge of digital design, computer architecture, and complex I/O designs.
  • Familiarity with UVM-based simulation environments and scripting skills are assets.

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