Emulation Verification Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$175,000–$308,500 / yr
Posted
1 day ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Salary context

Above market

How this pay compares to similar roles

Similar $194k
This role $242k
$131k $327k
below market most similar roles pay here above market

This role pays more than 87% of similar roles. Most pay $168,500–$219,500 — the blue band above. At the midpoint, this role pays about $242k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3564 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2760 roles with salary data.

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At a glance

TL;DR · Emulation Verification Engineer

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JOB TITLE: Emulation Verification Engineer The Emulation Verification Engineer joins the design verification team to focus on the creation, deployment, and support of sophisticated emulation environments for large SoCs. This role involves porting designs onto the Palladium platform and completing detailed emulation testplans. Key responsibilities include collaborating with Architecture, Design, Silicon Validation, Power, and SW teams to bring up large SoCs, developing synthesizable monitors, checkers, and stimulus, and performing low power testing. The candidate will develop code for design and verification using Verilog, SystemVerilog, and UVM, while building random stimulus infrastructure by reusing existing UVM simulation constraints. Required skills include experience with SystemVerilog assertions, C/C++ DPI, and scripting in Perl, Python, or TCL. The work involves managing the tool flow from RTL to Emulation.

Skills

SystemVerilog Verilog UVM Palladium Veloce Zebu Python Perl TCL C/C++ DPI FPGA Xilinx Altera RTL Design Verification Emulation SystemVerilog Assertions

What you'll do

  • Port large SoC designs onto the Palladium emulation platform.
  • Develop and apply synthesizable monitors, checkers, and stimulus on the emulation platform.
  • Prepare and complete detailed emulation test plans for multi-functional team reviews.
  • Perform low power testing on the emulation platform.
  • Develop Verilog, SystemVerilog, and UVM code to support emulation activities.
  • Develop random stimulus infrastructure by reusing existing UVM simulation constraints.
  • Write and debug test firmware to support verification efforts.

What we're looking for

  • Bachelor of Science degree and at least 10 years of relevant industry experience.
  • Proven design verification skills.
  • Experience writing synthesizable SystemVerilog/Verilog code and SystemVerilog assertions (preferred).
  • Experience with SystemVerilog verification environments including C/C++ DPI and UVM (preferred).
  • Experience with scripting in Perl, Python, or TCL (preferred).
  • Understanding of the tool flow from RTL to Emulation (preferred).
  • Good understanding of Standard Emulator (Palladium, Veloce, Zebu) or FPGA (Xilinx, Altera) flows (preferred).
  • Experience in UVM Acceleration (preferred).

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