Emulation Technical Leader

Cisco

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: San Jose, CA
Salary: $214,100–$309,800 / yr
Posted: 2 days ago
Freshness: Confirmed live today
Closes: Nov 17, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $210k

This role $262k

$149k most similar roles pay here $327k

This role pays more than 90% of similar roles. Most pay $186,637–$234,325 — the shaded band above. At the midpoint, this role pays about $262k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 193 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 193 roles with salary data.

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At a glance

TL;DR · Emulation Technical Leader

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The Emulation Technical Leader joins the Common Hardware Group to drive the DFT emulation strategy for Silicon One. This role involves architecting a pre-silicon emulation roadmap from scratch, building a high-performing engineering team, and establishing standards for validating complex scan, MBIST, and JTAG architectures. The successful candidate will collaborate with RTL, physical design, ATPG teams, and vendors to ensure seamless silicon bring-up for multi-terabit networks. Required technical skills include proficiency in Verilog, System Verilog, C/C++, and scripting languages such as Tcl, Python, or Perl. Experience is required with emulation platforms like Palladium, Veloce, or Zebu, along with compilation and debug capabilities. The role addresses the challenge of validating advanced ASIC designs for high-performance networking hardware, specifically focusing on the complex requirements of multi-terabit validation within a unified silicon architecture.

Skills

DFT Emulation Palladium Veloce Zebu Verilog System Verilog C C++ Tcl Python Perl JTAG MBIST Scan Architecture UVM Post Silicon validation ATPG

What you'll do

Architect the pre-silicon emulation roadmap from scratch for Silicon One products.
Define and lead the overall DFT emulation strategy for the engineering team.
Build and manage a high-performing engineering team focused on DFT emulation.
Validate complex scan, MBIST, and JTAG architectures on Palladium, Veloce, and Zebu platforms.
Coordinate with RTL, physical design, ATPG teams, and vendors to ensure seamless silicon bring-up.
Develop and maintain emulation flows using Verilog, SystemVerilog, and scripting languages like Tcl or Python.
Drive the validation of multi-terabit networking hardware at scale.

What we're looking for

Bachelor's degree plus 12 years of experience, Master's plus 8 years, or PhD plus 5 years of related experience.
Experience with emulation on platforms such as Palladium, Veloce, or Zebu including compilation and debug.
Proficiency in Verilog and System Verilog.
Proficiency in C/C++ and scripting skills using Tcl, Python, or Perl.
Experience defining DFT Emulation strategy (preferred).
Experience with JTAG protocol, scan architecture, MBIST, and boundary scan (preferred).
Knowledge of UVM and advanced System Verilog (preferred).
Post-silicon validation and/or debugging experience (preferred).

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