EDA Methodology Architect

Nvidia

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAAustin, TX
Salary: $168,000–$264,500 / yr
Employment: Full-time
Posted: 161 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $203k

This role $216k

$138k $278k

below market most similar roles pay here above market

This role pays more than 62% of similar roles. Most pay $168,515–$237,446 — the blue band above. At the midpoint, this role pays about $216k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · EDA Methodology Architect

Role Posting Log in to save

The Senior P&R Methodology Architect joins the team to define and own the next generation RTL2GDS flow for advanced nodes at 3nm and below for high performance GPU, CPU, and SoC designs. This role involves working with core P&R engine developers to shape requirements, defining next-gen flows, and refactoring legacy processes into scalable frameworks. Key responsibilities include running A/B experiments, performing root-cause analysis on timing closure issues, and developing analytics to mine large QoR datasets. The candidate must possess deep expertise in RTL, DFT, synthesis, placement, CTS, routing, and signoff using industry standard tools like ICC2/Innovus and PrimeTime/Tempus. Required skills include Python, Perl, and TCL flow development, alongside experience applying ML or GenAI techniques to physical design and flow development.

Skills

RTL2GDS Physical Design P&R Python TCL Perl ICC2 Innovus PrimeTime Tempus DFT Synthesis Placement CTS Routing Signoff Machine Learning GenAI EDA VLSI

What you'll do

Define and own the next-generation RTL2GDS flow for 3nm and below advanced nodes.
Define real-world optimization problems and shape requirements for core P&R engine developers.
Refactor legacy flows into scalable, maintainable frameworks used across multiple design teams.
Design and run rigorous A/B and multi-variant experiments to compare flows and tool settings.
Develop Python-based analytics and ML/GenAI techniques to mine large QoR datasets and automate analysis.
Perform deep root-cause analysis on timing closure and performance limiters across engines and tools.
Drive aggressive PPA and schedule targets while leading the adoption of new tools across the company.

What we're looking for

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
8+ years of physical design experience.
Deep expertise in industry standard tools like ICC2/Innovus and PrimeTime/Tempus.
Extensive hands-on P&R experience taking complex blocks or chips to tape-out with aggressive PPA targets.
Proven skills in Python, Perl, and TCL flow development.
Excellent communication and collaboration skills to drive consensus across distributed design, CAD, and R&D teams.
Experience collaborating with EDA or internal R&D teams on core engine development (preferred).
Hands-on experience applying AI/ML or GenAI to physical design, QoR analysis, or flow development (preferred).

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