EDA Methodology Architect

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CAAustin, TX
Salary
$168,000–$264,500 / yr
Posted
115 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $197k
This role $216k
$133k most similar roles pay here $279k

This role pays more than 67% of similar roles. Most pay $162,000–$232,812 — the shaded band above. At the midpoint, this role pays about $216k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · EDA Methodology Architect

As a Senior P&R Methodology Architect, you will join the team to define and own the next generation RTL2GDS flow for advanced nodes including 3nm and below for high performance GPU, CPU, and SoC designs. You will work with core engine developers to shape requirements, refactor legacy flows into scalable frameworks, and perform root-cause analysis on timing closure and performance limiters. Your daily work involves running A/B experiments, developing Python-based analytics, and applying ML or GenAI techniques to mine large QoR datasets. The role requires deep expertise in the full RTL2GDS flow including synthesis, placement, CTS, and routing. You must possess proficiency in industry standard tools like ICC2, Innovus, PrimeTime, and Tempus, alongside scripting skills in Python, Perl, and TCL to solve complex physical design challenges for advanced-node hardware.

What you'll do

  • Define and own the next generation RTL2GDS flow for advanced nodes and high-performance GPU, CPU, and SoC designs.
  • Collaborate with engine developers to define optimization problems, shape requirements, and provide feedback on tool behavior and scalability.
  • Refactor legacy flows and consolidate ad-hoc solutions into scalable, maintainable frameworks across multiple design teams.
  • Design and execute rigorous A/B and multi-variant experiments to compare different flows, engines, and tool settings.
  • Develop Python-based analytics and ML/GenAI techniques to mine QoR datasets and automate flow setting recommendations.
  • Perform deep root-cause analysis on timing closure and performance limiters to resolve complex "long tail" issues.
  • Drive aggressive PPA targets and the adoption of new tools and flows across the organization.

What we're looking for

  • BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
  • 8+ years of physical design experience.
  • Deep expertise in industry standard tools such as ICC2/Innovus and PrimeTime/Tempus.
  • Extensive hands-on P&R experience taking complex blocks or chips to tape-out with aggressive PPA targets.
  • Proven skills in Python, Perl, and TCL flow development.
  • Experience collaborating with EDA or internal R&D teams on core engine development and feature definition.
  • Expertise in designing A/B tests and using AI/ML or GenAI for physical design or QoR analysis.
  • Experience with advanced-node designs and challenges such as DFM, variability, EM/IR, and power integrity.

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