Analog Layout Automation Engineer

What you'll do

• Create high-performance analog and mixed-signal layouts using advanced CAD tools.
• Develop scripts in SKILL, Perl, TCL, or Python to automate layout tasks and workflows.
• Implement AI/ML techniques for layout optimization, verification acceleration, and data-driven design insights.
• Resolve LVS, DRC, and ERC issues to ensure physical verification compliance.
• Perform floor planning, hierarchical layout assembly, and physical integration for complex circuits.
• Develop and implement automated quality checks and intelligent metrics to reduce manual effort.
• Analyze circuit designs to address reliability concerns like IR drop, electromigration, and self-heating.
• Create and manage PCells and CAD automation workflows within the Cadence Virtuoso environment.

What we're looking for

• A BS degree in a technical discipline is required.
• Candidates must have at least 10 years of relevant experience.
• Experience designing analog and mixed-signal layouts in deep-submicron CMOS and FinFET technologies is preferred.
• Proficiency in scripting languages including SKILL, Perl, TCL, Shell, and/or Python for layout automation and data analysis is required.
• Knowledge of AI/ML concepts such as CNNs, loss functions, backpropagation, and PyTorch for model development is preferred.
• Experience with Cadence Virtuoso features, Cadence Innovus, and PCell creation is preferred.
• Ability to perform physical verification including DRC, ERC, and LVS analysis is required.
• Proficiency in floor planning, hierarchical layout assembly, and understanding of reliability concerns like IR drop and electromigration is preferred.