Analog Layout Automation Engineer

Apple Inc

Confirmed live 2 days ago Low trust

Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$175,500–$311,700 / yr
Posted
143 days ago
Freshness
Confirmed live 2 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $179k
This role $244k
$119k most similar roles pay here $332k

This role pays more than 90% of similar roles. Most pay $144,450–$213,531 — the shaded band above. At the midpoint, this role pays about $244k versus about $179k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Analog Layout Automation Engineer

As an Analog Layout Automation Engineer within the Silicon Engineering Group, you will convert design concepts into silicon by creating high-performance analog and mixed-signal layouts for systems-on-chip including SerDes, PLLs, and sensors. You will collaborate with circuit designers to review floor plans, run verification suites, and resolve LVS, DRC, and ERC issues. A primary focus of this role is driving automation through script development, workflow improvements, and the application of AI/ML techniques for layout optimization, verification acceleration, and data-driven design insights. Required skills include proficiency in SKILL, Perl, TCL, Shell, and Python, along with experience in PyTorch, CNNs, and image processing fundamentals. You will utilize Cadence Virtuoso and Innovus to manage complex physical integration while addressing technical challenges like IR drop, RC delay, and electromigration in deep-submicron CMOS and FinFET technologies.

What you'll do

  • Convert design concepts into high-performance analog and mixed-signal layouts using advanced CAD tools.
  • Develop scripts in SKILL, Perl, TCL, or Python to automate layout tasks and workflows.
  • Apply AI/ML techniques to optimize layouts, accelerate verification, and provide data-driven design insights.
  • Resolve LVS, DRC, and ERC issues to ensure physical integrity of the silicon designs.
  • Perform floor planning, hierarchical layout assembly, and physical integration for complex SOCs.
  • Implement automated quality checks and advanced modeling to reduce manual effort in the design cycle.
  • Analyze circuit structures to address reliability concerns like IR drop, electromigration, and coupling capacitance.

What we're looking for

  • Bachelor's degree in a technical discipline.
  • Minimum of 10 years of relevant experience.
  • Experience designing analog and mixed-signal layouts in deep-submicron CMOS and FinFET technologies.
  • Proficiency in scripting languages including SKILL, Perl, TCL, Shell, and/or Python for layout automation and data analysis.
  • Knowledge of AI/ML concepts such as CNNs, loss functions, backpropagation, and PyTorch for model development.
  • Experience with Cadence Virtuoso features, Innovus, and CAD automation workflows like PCell creation.
  • Ability to resolve physical verification issues including DRC, ERC, and LVS.
  • Understanding of layout reliability concerns such as IR drop, RC delay, electromigration, and self-heating.

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