This role pays more than
98%
of similar roles. Most pay
$168,500–$229,100
— the shaded band above.
At the midpoint, this role pays about
$255k
versus about
$199k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3553 open roles
on FindRole.
Listed pay typically runs
$165,800–$277,600
across 2740 roles with salary data.
As a Design Verification Engineer, you will join the hardware team to ensure bug-free first silicon for SoC and IP designs. You will be responsible for all phases of pre-silicon verification, including establishing methodologies, developing test plans based on micro-architecture, and building scalable, portable verification environments. Your daily work involves creating stimulus, checkers, assertions, and trackers while managing coverage and sign-off for RTL freeze and tape-out. To achieve these goals, you will utilize SystemVerilog, UVM, and scripting languages like Python, Perl, or TCL. You will also leverage LLMs to improve execution efficiency and quality. The role focuses on the technical challenge of validating complex hardware components through regression testing, debug, and gate level simulations to ensure functional integrity before production.
What does a Design Verification Engineer earn in California?
Median $189224 from 46 postings across 7 companies.
Develop comprehensive test plans and verification methodologies based on micro-architecture specifications.
Build scalable and portable verification environments using SystemVerilog and UVM.
Create stimulus, checkers, assertions, and trackers to stress the design.
Execute verification plans including design bring-up and regression testing.
Debug test failures and resolve bugs found during the verification process.
Track and report progress using metrics such as bug counts and coverage data.
Utilize LLMs and related technologies to improve verification efficiency and quality.
Ensure bug-free first silicon through all phases of pre-silicon verification and sign-off.
What we're looking for
BS degree in a technical subject area.
Minimum of 10 years of relevant industry experience.
Deep knowledge of OOP, SystemVerilog, and UVM (preferred).
Deep knowledge in developing scalable and portable test-benches (preferred).
Strong experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, and gate level simulations (preferred).
Experience using LLMs for efficiency and quality (preferred).
Experience with power-aware (UPF) or similar verification methodology (preferred).
Excellent knowledge of scripting languages such as Python, Perl, or TCL (preferred).