Design Verification

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$150,400–$225,300 / yr
Posted
43 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $209k
This role $188k
$139k $253k
below market most similar roles pay here above market

This role pays less than 54% of similar roles. Most pay $176,493–$241,750 — the blue band above. At the midpoint, this role pays about $188k versus about $209k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

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At a glance

TL;DR · Design Verification

The Design Verification role involves performing low power verification for various Apple SOCs. You will review power related aspects of design and architecture specifications for SOCs and corresponding Power Manager SOCs while collaborating with design, architecture, and software teams to identify testable attributes. Key responsibilities include developing test plans, coverage plans, and test benches to verify low power functionality and hardware state restoration during power state transitions. You will create directed and random tests, write C programming tests, and develop System Verilog behavioral models and stimulus. Automation tasks will require Perl and Python scripts for regression maintenance and failure triaging. You will also use CAD software for chip level simulations, utilize AXI and AMBA protocols for block integration, and apply UPF for describing power intent.

What you'll do

  • Perform low power verification for various Apple System on Chips (SoCs).
  • Develop test plans and coverage plans to verify low power functionality and hardware state restoration.
  • Create test benches, behavioral models, and stimulus using SystemVerilog and C.
  • Write Perl and Python scripts to automate test plan execution, failure triaging, and regression maintenance.
  • Run chip-level simulations using CAD software to verify block integration.
  • Debug failing test cases using AXI and AMBA protocols.
  • File and track bug reports for simulation failures until final closure.

What we're looking for

  • Bachelor’s Degree or foreign equivalent in Computer Science, Computer Engineering, or a related field.
  • 2 years of experience in the job offered or a related occupation.
  • 2 years of experience using digital and logic design concepts to understand hardware design and verification.
  • 2 years of experience utilizing ARM/X86 based computer architecture to drive processor-based verification stimulus.
  • 2 years of experience using data structures and algorithms to write efficient C-based stimulus for chip-level verification.
  • 2 years of experience utilizing SystemVerilog to create stimulus and behavioral models to validate chip design systems.
  • 2 years of experience using C to write chip-level test cases that drive stimulus.
  • 2 years of experience utilizing Perl or Python to automate tasks like running test cases, failure triaging, and regression maintenance.
  • 2 years of experience utilizing low power design fundamentals specific to CMOS-based designs.
  • 2 years of experience using languages including UPF to describe power intent for hardware designs.

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