Design Engineer - Timing Methodology

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$143,800–$230,000 / yr
Employment
Full-time
Posted
51 days ago
Freshness
Confirmed live yesterday
Closes
Feb 15, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $208k
This role $187k
$129k most similar roles pay here $279k

This role pays less than 58% of similar roles. Most pay $171,125–$245,200 — the shaded band above. At the midpoint, this role pays about $187k versus about $208k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 228 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 158 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · Design Engineer - Timing Methodology

The Design Engineer - Timing Methodology joins the Timing Sign-Off group within Central Engineering to develop advanced timing sign-off methodologies for SOC and 3D/2.5D IC designs. This role involves taking ownership of methodology development, modeling, and complex studies of new concepts to improve existing solutions for high yield and optimized margins. The candidate will design and implement multi-die signoff solutions while leading EDA flow development for Primetime, Tempus, and Innovus. Required technical skills include proficiency in TCL, Python, Perl, and Unix shell for script development and flow automation, alongside experience with revision control and continuous integration tools. The role addresses the challenge of achieving high yield at advanced technology nodes through statistical data analysis, modeling, and deep knowledge of silicon technologies and production testability within a fast-paced project oriented agile environment.

What you'll do

  • Develop and deploy timing signoff methodologies for advanced technology nodes.
  • Design and implement signoff solutions for SOC, 3D/2.5D IC, and multi-die designs.
  • Lead the development of EDA flows using Primetime, Tempus, and Innovus tools.
  • Perform complex studies and analysis of new concepts to improve existing timing solutions.
  • Conduct statistical data analysis and modeling to optimize yield and production testability.
  • Develop scripts in TCL, Python, Perl, and Unix shell for flow automation.
  • Manage project lifecycles using revision control, issue tracking, and continuous integration tools.

What we're looking for

  • A BS degree in EE/CS with 12+ years of industry experience is required.
  • An MS or PhD degree in EE/CS with 10+ years of industry experience is required.
  • Experience in timing signoff methodology development and ownership for SOC and 3D/2.5D IC designs is required.
  • Experience in advanced silicon technologies, production testability, and yield is required.
  • Experience with tapeouts for high volume, high yield complex SOCs at advanced technology nodes is required.
  • Proficiency with industry standard STA tools such as Primetime and Tempus is required.
  • Experience developing scripts in TCL, Python, Perl, Unix shell, and flow automation is required.
  • Experience with revision control, issue management, CI/CD, and defect tracking tools is required.

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