Design Engineer - Chip Floorplanner

Broadcom

Quick summary

Work type: On-site
Location: Fort Collins, CO
Salary: $127,100–$203,400 / yr
Posted: 25 days ago
Closes: Nov 6, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $186k

This role $165k

$116k most similar roles pay here $231k

This role pays less than 67% of similar roles. Most pay $155,275–$216,250 — the shaded band above. At the midpoint, this role pays about $165k versus about $186k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 61 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 60 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Design Engineer - Chip Floorplanner

Apply Now Log in to save

Join Broadcom’s Custom Silicon Design Team as a Floorplanning Engineer, contributing to the development of cutting-edge AI, Cellular, Networking, Computing, and Storage ASICs. This role involves defining and optimizing chip-level physical architecture for high-performance SoCs operating at speeds exceeding 1 GHz, from concept through production. Day-to-day responsibilities include floorplan definition, macro placement, power grid design, and collaboration with RTL, timing, and packaging teams to balance performance, power, and area targets. Essential skills encompass VLSI design principles, TCL scripting, Linux environments, and proficiency in Python or similar languages. Familiarity with Cadence tools is a plus. This position requires strong communication and problem-solving abilities, as well as the capacity to mentor others and lead initiatives across global teams.

Skills

TCL Linux Python Perl Ruby Cadence VLSI ASIC floorplanning die partitioning hierarchical design PLLs clock networks power delivery timing-critical structures physical verification DRC LVS congestion analysis power analysis PPA optimization

What you'll do

Define and optimize top-level floorplan architecture for advanced ASICs.
Drive macro placement, power grid design, and clock distribution planning.
Lead top-level timing closure and congestion analysis to ensure tapeout readiness.
Coordinate with block owners for smooth integration from block-level to top-level.
Apply deep understanding of physical verification and IR/EM analysis for signoff-quality results.
Contribute to the development of advanced process technology design methodologies.

What we're looking for

At least 10 years of experience in VLSI design or equivalent MS degree.
Expertise in floorplanning, die partitioning, hierarchical design, and PPA optimization.
Proficiency in TCL scripting and Linux environments; Python, Perl, Ruby preferred.
Experience with Cadence or similar physical design tools for advanced process nodes.
Strong collaboration skills and ability to work across global teams effectively.

Similar roles

Design Engineer

Broadcom

Fort Collins, CO 101 days ago $60,200–$96,300

UNIX Linux TCL Python Perl Cadence_Innovus Synopsys_ICC2 PrimeTime VLSI CMOS_logic digital_circuit_fundamentals floorplanning placement routing timing_closure physical_verification DRC LVS block_level_integration EDA_tools

Save

ASIC Design Engineer

Broadcom

Irvine, CA 65 days ago $108,000–$172,800

EDA Synthesis Design_for_Test Floorplanning Place_and_Route Clock_Methodology Power_Planning_Analysis Timing_Closure Signal_Integrity Physical_Design_Checks

Save

Processor Micro Architect RTL Design Engineer (Multiple Levels)

Qualcomm

San Diego, CA 29 days ago $180,400–$270,600

Verilog System Verilog RTL digital design logic design cache memory coherency bus interface multi-core microprocessor architecture low power design functional verification static timing analysis formal verification PLDRC clock domain crossing

Save

R&D IC Design Engineer

Broadcom

Irvine, CA 159 days ago $141,300–$226,000

Verilog VHDL Python C Unix Perl RTL simulation synthesis FEC design digital signal processing high speed digital circuit design ARM subsystem 10G/100G/200G/400G/800G Ethernet OTN network design for low power design for test design for manufacturing

Save

Senior ASIC Floorplan Design Engineer

Nvidia

Santa Clara, CA 16 days ago $196,000–$310,500

Verilog SystemVerilog Python Perl C++ CAD VLSI ComputerArchitecture ChipFloorplan PowerClockDistribution Packaging P&R TimingClosure

Save

Hardware Board Design Engineer

Qualcomm

Santa Clara, CA 30 days ago $180,500–$270,700

OrCAD Cadence Allegro PCIe DDR Ethernet SerDes SIPI PDN EMI Python TCL Perl Oscilloscopes Logic analyzers Protocol analyzers High-speed design High-power design MULTILAYER PCBs Cross-functional collaboration Technical documentation

Save