R&D IC Design Engineer

Broadcom

Quick summary

Work type: On-site
Location: Irvine, CA · San Jose, CA
Salary: $141,300–$226,000 / yr
Posted: 159 days ago
Closes: Jun 18, 2026

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $183k

This role $184k

$125k most similar roles pay here $237k

This role pays more than 60% of similar roles. Most pay $152,875–$213,375 — the shaded band above. At the midpoint, this role pays about $184k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 61 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 60 roles with salary data.

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At a glance

TL;DR · R&D IC Design Engineer

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Senior Design Engineer position available for a team focused on developing chips for high-speed optical communication systems. The role involves architecting block-level designs from marketing and system requirements, preparing detailed design documents, conducting RTL coding, performing lint checks, CDC, synthesis, and equivalency checking, as well as scripting for various IC design tasks. Responsibilities include generating verification and test plans, analyzing power consumption and die size trade-offs, and supporting silicon bring-up and validation processes. Candidates should have a B.S. or M.S./Ph.D. in EE or Computer Engineering with relevant experience, strong knowledge of ARM subsystems, high-speed digital circuits, and Ethernet standards up to 800G. Proficiency in Verilog, VHDL, Unix/Perl scripting, Python, and C is essential, along with expertise in low-power design and manufacturing procedures. Ideal candidates will possess excellent analytical skills, hands-on debugging experience, and the ability to collaborate effectively across remote teams.

Skills

Verilog VHDL Python C Unix Perl RTL simulation synthesis FEC design digital signal processing high speed digital circuit design ARM subsystem 10G/100G/200G/400G/800G Ethernet OTN network design for low power design for test design for manufacturing

What you'll do

- Architect block level design specifications from marketing or system requirements.
- Prepare detailed design documents, timing constraint files, and verification/test plans.
- Perform RTL coding, lint checks, CDC, synthesis, equivalency checking, STA, simulations, and silicon debug.
- Script for various IC design tasks such as STA, equivalency checks, test bench creation, and simulations.
- Conduct design tradeoff analysis focusing on power consumption, die size, schedule, resource allocation.

What we're looking for

Minimum 6 years of experience in EE or Computer Engineering, M.S/Ph.D preferred.
Expertise in high-speed digital circuit design, including ARM subsystems and FEC.
Proficiency in RTL coding, simulation, synthesis, and scripting for IC tasks.
Strong analytical skills with hands-on lab debugging experience.
Knowledge of low power design, testability, and manufacturing procedures.
Understanding of the entire IC development flow from concept to production.

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