Custom Timing and Verification CAD Engineer

Apple Inc

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Work type: On-site
Location: Austin, TX
Posted: 130 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3564 open roles on FindRole.

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TL;DR · Custom Timing and Verification CAD Engineer

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JOB TITLE: Custom Timing and Verification CAD Engineer The Custom Timing CAD team seeks an entry-level engineer to develop and maintain flows for critical sign-off disciplines in custom IC design. You will support analog and digital designers across various technology nodes by setting up timing and verification runs, interpreting results, and resolving tool issues. Your daily work involves developing automation scripts and improving flow efficiency for transistor-level timing verification using NanoTime and formal verification using ESP. You will also contribute to methodology documentation and engage with EDA vendors to evaluate new features. Required skills include programming in Perl, Python, or TCL, alongside a solid understanding of transistor-level custom IC design and static timing analysis. You will work with SPICE netlists, device models, and parasitic extraction formats like DSPF or SPF.

Skills

NanoTime ESP Python Perl TCL Static Timing Analysis Formal Verification PrimeTime HSPICE SystemVerilog SPICE DSPF SPF RTL-to-schematic equivalence checking Mixed-signal circuit techniques GenAI

What you'll do

Develop, maintain, and improve CAD flows and automation scripts for NanoTime and ESP.
Support design teams in setting up timing and verification runs and interpreting results.
Resolve tool and methodology issues to drive timing and formal verification closure.
Contribute to methodology documentation and guidelines for various design organizations.
Engage with EDA vendors to report issues and evaluate new tool features.
Build automation to improve flow efficiency and reduce runtime across concurrent programs.

What we're looking for

Minimum of a BS degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Minimum of 10 years of relevant industry experience.
Strong programming or scripting experience in Perl, Python, TCL, or similar languages.
Solid understanding of digital or custom IC design at the transistor level and static timing analysis.
Hands-on experience with transistor-level timing and formal verification tools such as NanoTime, ESP, PrimeTime, or HSPICE (preferred).
In-depth knowledge of dynamic logic, memory arrays, or mixed-signal circuit techniques (preferred).
Experience with SPICE netlists, device models, and parasitic extraction formats such as DSPF or SPF (preferred).
Experience with formal verification methodologies and SystemVerilog RTL (preferred).