Custom Timing and Verification CAD Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $184,700–$324,800 / yr
Posted: 130 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k

This role $255k

$129k $346k

below market most similar roles pay here above market

This role pays more than 98% of similar roles. Most pay $174,950–$229,100 — the blue band above. At the midpoint, this role pays about $255k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3564 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2760 roles with salary data.

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At a glance

TL;DR · Custom Timing and Verification CAD Engineer

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The Custom Timing and Verification CAD Engineer joins the Custom Timing CAD team to support and develop critical flows for transistor-level timing verification and formal verification. This entry-level role involves developing, maintaining, and improving CAD flows and automation scripts for NanoTime and ESP. The engineer will partner with analog and digital designers to set up runs, debug issues, and achieve sign-off across multiple technology nodes. Key responsibilities include driving verification closure, contributing to methodology documentation, and engaging with EDA vendors to evaluate new features. Required skills include programming in Perl, Python, or TCL, alongside a solid understanding of digital or custom IC design at the transistor level and static timing analysis. The work addresses the technical challenge of ensuring rigorous timing verification for sophisticated custom silicon.

Skills

NanoTime ESP Python Perl TCL Static Timing Analysis Formal Verification PrimeTime HSPICE SystemVerilog SPICE DSPF SPF RTL-to-schematic equivalence checking AI/ML GenAI

What you'll do

Develop, maintain, and improve CAD flows and automation scripts for NanoTime and ESP.
Support design teams in setting up timing and verification runs and interpreting results.
Resolve tool and methodology issues to drive timing and formal verification closure.
Contribute to methodology documentation and guidelines adopted across design organizations.
Engage with EDA vendors to report issues and evaluate new tool features.
Build automation to improve flow efficiency and reduce runtime across concurrent programs.

What we're looking for

Minimum of BS degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Minimum of 10 years relevant industry experience.
Strong programming or scripting experience in Perl, Python, TCL, or similar language.
Solid understanding of digital or custom IC design at transistor level and static timing analysis.
Hands-on experience with transistor-level timing and formal verification tools such as NanoTime, ESP, PrimeTime, or HSPICE (preferred).
In-depth knowledge of dynamic logic, memory arrays, or mixed-signal circuit techniques (preferred).
Experience with SPICE netlists, device models, and parasitic extraction formats (preferred).
Experience with formal verification methodologies and SystemVerilog RTL (preferred).

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