CPU Design Timing Engineer

Apple Inc

Confirmed live yesterday Low trust

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Work type: On-site
Location: Beaverton, OR
Posted: 126 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Similar $210k

$137k $277k

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This listing doesn't post a salary. Most similar roles pay $177,087–$242,862.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · CPU Design Timing Engineer

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The CPU Design Timing Engineer joins the Silicon Engineering Group to focus on CPU block-level implementation. This role is responsible for the timing closure of the project, which involves collaborating with the CAD team to develop timing flows and writing scripts to improve analysis efficiency. The engineer works extensively with CPU micro-architects and implementation engineers to drive timing closure for high performance CPU designs. Key responsibilities include managing multiple clock and power domains for 1 ghz+ designs while addressing crosstalk, noise, OCV, uncertainty, and derate methodology. Required technical skills include proficiency with static timing tools like Primetime or Tempus, along with script writing and debugging in TCL, Perl, or Python. The role also requires knowledge of physically aware synthesis, place and route tools, and physical design verification.

Skills

Primetime Tempus TCL Python Perl Physical Design Place & Route Physically Aware Synthesis LEC DVS Cross Talk OCV Extraction Scripting

What you'll do

Drive timing closure for high-performance CPU designs.
Develop timing flows and scripts to improve analysis efficiency with the CAD team.
Coordinate with micro-architects and implementation engineers to resolve timing issues.
Manage timing for designs exceeding 1 GHz with multiple clock and power domains.
Apply methodologies for crosstalk, noise, OCV, uncertainty, and derate.
Utilize static timing tools such as Primetime or Tempus for analysis.
Perform physical design verification including LEC and DVS.

What we're looking for

Minimum BS degree and 10+ years of relevant industry experience.
Experience working on timing for 1 ghz+ designs, including multiple clock and power domains.
Experience with static timing tools such as Primetime or Tempus.
Experience with cross talk, noise, OCV, uncertainty, and derate methodology.
Experience with script writing and debugging in TCL, Perl, or Python.
Implementation experience on high performance CPU designs (preferred).
Working knowledge of CPU microarchitecture, including critical loops and low power techniques (preferred).
Good understanding of physical design tools, methodology, and verification (preferred).