CAD Engineer, Silicon Learning and Static Timing Analysis

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $150,400–$277,600 / yr
Posted: 10 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $210k

This role $214k

$135k most similar roles pay here $293k

This role pays more than 54% of similar roles. Most pay $177,250–$242,775 — the shaded band above. At the midpoint, this role pays about $214k versus about $210k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2240 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1831 roles with salary data.

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At a glance

TL;DR · CAD Engineer, Silicon Learning and Static Timing Analysis

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As a CAD Engineer, Silicon Learning and Static Timing Analysis within the Silicon Technologies group, you will analyze silicon performance data to improve static timing analysis tools, flows, margins, and design closure methodologies. You will collaborate with design, DFT, CAD, and product engineering teams to design experiments, mine data to establish correlation metrics for design closure activities, and develop methodologies to optimize power and performance tradeoffs. The role requires proficiency in C, Perl, Python, or Tcl, alongside knowledge of statistics, hypothesis testing, data mining, Machine Learning, and Design of Experiments. You will work on advanced semiconductor technology nodes to address challenges in high-performance, power-efficient system-on-chip designs. Preferred experience includes Static Timing Analysis with Primetime or Tempus, physical design, failure analysis, and exposure to tools like Tetramax or Tessent for silicon debug.

Skills

Static Timing Analysis Python Tcl Perl C Primetime Tempus DFT Design of Experiments Machine Learning Data Mining Silicon Debug Tetramax Tessent Physical Design Semiconductor Processing

What you'll do

Analyze silicon performance data to identify key metrics and trends.
Incorporate silicon learnings into static timing analysis tools, flows, and design closure methodologies.
Mine and analyze silicon data to establish correlation metrics for design closure activities.
Develop and deploy design closure margins to optimize power and performance tradeoffs.
Design experiments and analyze results in collaboration with design, DFT, CAD, and product engineering teams.
Refine design methodologies applied across all silicon designs at the company.
Utilize coding skills in C, Perl, Python, or Tcl to debug and solve design challenges.

What we're looking for

Bachelor of Science degree and 3 years of relevant industry experience.
Coding experience in one or more of C, Perl, Python, or Tcl.
Experience in static timing analysis, DFT, physical design, failure analysis, or CAD (preferred).
Static Timing Analysis with Primetime, Tempus, or equivalent (preferred).
Advanced coding and debugging skills coupled with an understanding of advanced technology node challenges (preferred).
Knowledge of statistics, hypothesis testing, data mining, Machine Learning, and Design of Experiments (preferred).
Prior exposure to DFT, Tetramax, Tessent, silicon debug, or semiconductor processing (preferred).