CAD Engineer, Timing for Gate-Level Flows & Methodologies

What you'll do

• Develop, maintain, and enhance gate-level static timing analysis (STA) flows for silicon designs.
• Debug issues related to constraints, flow scripts, and timing closure with design teams.
• Drive methodology changes to improve efficiency, productivity, and silicon timing correlation.
• Create and maintain scripts and methods for timing analysis and power reduction.
• Develop tools and methodologies to verify timing constraints and establish best practices.
• Analyze timing paths to identify critical issues and perform post-silicon timing debug.
• Collaborate with EDA vendors to develop and integrate new capabilities to solve technical problems.

What we're looking for

• Bachelor of Science degree and 10 years of relevant industry experience.
• Expert power user of static timing analysis tools and flows (preferred).
• Advanced programming skills with Python, Tcl, or other high-level languages (preferred).
• Proven track record of development and deployment of complex CAD flows and automation (preferred).
• Familiarity with STA of large high-performance SoC designs in deep sub-micron technologies (preferred).
• Deep understanding of noise, cross-talk, variation, margins, and timing models (preferred).
• Knowledge of timing/SDC constraints and hands-on experience in creation and validation of constraints (preferred).
• Excellent communicator capable of assessing issues for management and following solutions to completion (preferred).