CAD Engineer - Timing for Gate-Level Flows & Methodologies

Apple Inc

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Quick summary

Work type
On-site
Location
—
Salary
$184,700–$324,800 / yr
Posted
15 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $255k
$129k most similar roles pay here $346k

This role pays more than 93% of similar roles. Most pay $177,250–$227,500 — the shaded band above. At the midpoint, this role pays about $255k versus about $202k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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TL;DR · CAD Engineer - Timing for Gate-Level Flows & Methodologies

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CAD Engineer - Timing for Gate-Level Flows & Methodologies will join the STA CAD team to improve the performance of Apple Silicon. The role involves developing, maintaining, and enhancing gate-level static timing analysis flows while addressing timing challenges on advanced technology nodes. Key responsibilities include creating scripts for timing analysis and power reduction, debugging constraints and flow scripts with design teams, and driving methodology changes to improve efficiency and silicon timing correlation. The candidate will also work with EDA vendors to incorporate new capabilities and perform post-silicon timing debug. Required skills include expert proficiency in static timing analysis tools, advanced programming in Python and Tcl, and a deep understanding of noise, cross-talk, variation, margins, and timing models. This role focuses on the technical challenge of ensuring first time right silicon for high-performance SoC designs.

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