CAD Engineer, Silicon Learning and Static Timing Analysis

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $216,200–$394,000 / yr
Posted: 11 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $210k

This role $305k

$138k most similar roles pay here $421k

This role pays more than 99% of similar roles. Most pay $177,250–$241,937 — the shaded band above. At the midpoint, this role pays about $305k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2240 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1831 roles with salary data.

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At a glance

TL;DR · CAD Engineer, Silicon Learning and Static Timing Analysis

Role Posting Log in to save

As a CAD Engineer, Silicon Learning and Static Timing Analysis within the Silicon Technologies group, you will analyze silicon performance data to improve static timing analysis tools, flows, margins, and design closure methodologies. You will collaborate with design, DFT, CAD, and product engineering teams to design experiments, analyze results, and refine design methodologies across all silicon designs. Your work involves mining and analyzing silicon data to establish correlation metrics for design closure activities while developing methodologies to optimize power and performance tradeoffs on leading edge semiconductor technology nodes. The role requires proficiency in C, Perl, Python, or Tcl coding and debugging. Preferred skills include experience with Primetime, Tempus, Tetramax, Tessent, and fundamentals of statistics, hypothesis testing, data mining, Machine Learning, and Design of Experiments to solve complex challenges in advanced silicon design.

Skills

Static Timing Analysis CAD DFT Python Tcl Perl C Machine Learning Design of Experiments Data Mining Primetime Tempus Tetramax Tessent Physical Design Silicon Debug

What you'll do

Analyze silicon performance data to improve static timing analysis tools, flows, and design closure methodologies.
Design experiments and analyze results in collaboration with design, DFT, CAD, and product engineering teams.
Drive the adoption of new technologies within the field of static timing analysis.
Mine and analyze silicon data to establish correlation metrics for design closure activities.
Develop and deploy design closure margins to optimize power and performance tradeoffs.
Implement advanced techniques to improve battery life and performance on leading-edge semiconductor nodes.

What we're looking for

Bachelor of Science degree and 20 years of relevant industry experience.
Coding experience in one or more of C, Perl, Python, or Tcl.
Experience in static timing analysis, DFT, physical design, failure analysis, or CAD (preferred).
Proficiency with Primetime, Tempus, or equivalent tools for Static Timing Analysis (preferred).
Advanced coding and debugging skills in C, Perl, Python, or Tcl with an understanding of advanced technology nodes (preferred).
Knowledge of statistics, hypothesis testing, data mining, Machine Learning, and Design of Experiments (preferred).
Prior exposure to DFT, Tetramax, Tessent, silicon debug, or semiconductor processing (preferred).