CAD Engineer, Silicon Learning and Static Timing Analysis

What you'll do

• Analyze silicon performance data to improve static timing analysis tools, flows, and design closure methodologies.
• Mine and analyze silicon data to establish correlation metrics for design closure activities.
• Develop and deploy design closure margins to optimize power and performance tradeoffs.
• Design experiments and analyze results in collaboration with design, DFT, CAD, and product engineering teams.
• Refine design methodologies applied across all silicon designs at the company.
• Implement advanced technology node optimizations to improve battery life and device performance.

What we're looking for

• Bachelor of Science degree and at least 10 years of relevant industry experience.
• Coding experience in one or more of C, Perl, Python, or Tcl.
• Experience in static timing analysis, DFT, physical design, failure analysis, or CAD (preferred).
• Static Timing Analysis with Primetime, Tempus, or equivalent tools (preferred).
• Advanced coding and debugging skills in C, Perl, Python, or Tcl with an understanding of advanced technology nodes (preferred).
• Knowledge of statistics, hypothesis testing, data mining, Machine Learning, and Design of Experiments (preferred).
• Prior exposure to DFT, Tetramax, Tessent, silicon debug, or semiconductor processing (preferred).