CAD Engineer on ML/AI for Design Verification

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$164,000–$246,000 / yr
Posted
60 days ago
Freshness
Confirmed live yesterday
Closes
Jan 9, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $195k
This role $205k
$139k most similar roles pay here $257k

This role pays more than 57% of similar roles. Most pay $168,425–$222,250 — the shaded band above. At the midpoint, this role pays about $205k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · CAD Engineer on ML/AI for Design Verification

As a CAD Engineer on ML/AI for Design Verification, you will join the ASICS Engineering team to develop automation tools and flows specifically for design verification. Your daily responsibilities include enabling state of the art EDA tools, creating comprehensive documentation for automation processes, and conducting research to integrate the latest machine learning and artificial intelligence technologies into existing workflows. You will collaborate with cross-functional teams to solve complex problems and improve overall productivity. The role requires proficiency in programming languages including Python, Perl, TCL, GNU Make, and JavaScript. Candidates should possess experience in CAD, design verification, or related domains, with a focus on VLSI design and verification. This position addresses the technical challenge of enhancing the efficiency and reliability of automated flows within the semiconductor design verification domain.

What you'll do

  • Develop and optimize CAD tools and flows to improve design verification productivity and efficiency.
  • Enable state-of-the-art EDA tools for the internal design verification teams.
  • Research and integrate machine learning and AI technologies into existing DV workflows.
  • Create and maintain detailed documentation for all automation processes and tools.
  • Identify and implement improvements in automation processes through cross-functional collaboration.
  • Propose and execute innovative solutions to complex technical problems in CAD automation.

What we're looking for

  • Bachelor's degree in Science, Engineering, or a related field.
  • Master's degree in Science, Engineering, or a related field.
  • PhD in Science, Engineering, or a related field.
  • 8+ years of experience in CAD, DV, or related domains.
  • 6+ years of experience in ASIC design, verification, validation, integration, or related work for Bachelor's degree holders.
  • 5+ years of experience in ASIC design, verification, validation, integration, or related work for Master's degree holders.
  • 4+ years of experience in ASIC design, verification, validation, integration, or related work for PhD holders.
  • Proficiency in programming languages including Python, Perl, TCL, GNU Make, and JavaScript.

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