SR ASIC Design Engineer - Networking/ DPU/ AI Systems in Santa Clara, California | Advanced Micro Devices, Inc

Amd

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $200,000–$200,000 / yr
Posted: 17 days ago
Closes: May 26, 2027
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $191k

This role $200k

$152k most similar roles pay here $233k

This role pays more than 57% of similar roles. Most pay $166,162–$216,250 — the shaded band above. At the midpoint, this role pays about $200k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 71 open roles on FindRole.

Listed pay typically runs $178,400–$178,400 across 71 roles with salary data.

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At a glance

TL;DR · SR ASIC Design Engineer - Networking/ DPU/ AI Systems in Santa Clara, California | Advanced Micro Devices, Inc

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The Senior ASIC Design Engineer role within NTSG involves developing advanced system solutions that integrate ASICs, hardware, and software for next-generation AI networking workloads. This position requires hands-on experience across the entire ASIC development cycle, from RTL architecture through tapeout to mass production. Day-to-day responsibilities include architecting key blocks for DPU ASICs, collaborating on network processing engines, and ensuring functional correctness with verification teams. The ideal candidate possesses strong skills in Verilog and SystemVerilog, along with C/C++ programming, Python, Tcl, and Shell scripting. Experience with ARM or RISC-V SoC ASIC design, Network-on-Chip architectures, and AXI/AMBA protocols is preferred, as well as familiarity with P4 for programmable packet processing. This role demands a self-motivated individual capable of tackling complex technical challenges in a fast-paced environment.

Skills

Verilog SystemVerilog C C++ Python Tcl Shell P4 AXI AMBA RTL ASIC SoC NoC Network-on-Chip

What you'll do

Architect and design key blocks for next-generation DPU ASICs targeting AI networking workloads.
Design and implement high-speed, complex ASIC blocks for networking and data movement applications.
Debug and resolve issues across simulation, emulation, lab bring-up, and post-silicon phases.
Contribute to performance, power, and area optimization of ASIC designs.
Support integration of ASIC IPs into larger SoC and system architectures.
Work closely with verification, modeling, software, and hardware teams for functional correctness.

What we're looking for

Experienced in developing high-speed, complex ASICs
Proven hands-on experience across the full ASIC development cycle
Strong background in networking and packet-processing architectures
Expertise in RTL design using Verilog and SystemVerilog
Programming skills in C/C++ and scripting with Python, Tcl, Shell
Bachelor’s or Master’s degree in Electrical/Computer Engineering

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