ASIC/SoC Design Engineer, RTL design for SoC IPs

Amd

Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Posted
128 days ago
Closes
Feb 26, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $188k
$133k most similar roles pay here $235k

This listing doesn't post a salary. Most similar roles pay $160,000–$216,250.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 56 open roles on FindRole.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · ASIC/SoC Design Engineer, RTL design for SoC IPs

Role Posting Log in to save

As a Senior ASIC Design Engineer at AMD's Silicon Design team, you will lead the RTL design lifecycle of cutting-edge IPs for next-generation embedded products, from micro-architecture specification to production silicon. Your daily tasks include Verilog RTL coding, timing closure, and physical design collaboration, ensuring compliance with PPA targets and industry-standard protocols like AMBA AXI/AHB/APB. You will drive full ASIC development through all phases, integrate complex IP blocks into SOC designs, and work closely with verification teams to ensure comprehensive functional coverage. Essential skills include expert Verilog RTL coding, experience with the complete ASIC design flow, and hands-on knowledge of SDC timing constraints. Preferred qualifications involve familiarity with PCIe or CXL protocols, scripting languages like Python or Perl, and mentoring junior engineers in a fast-paced environment.

Skills

Verilog RTL PrimeTime Tempus SDC AMBA AXI AMBA AHB AMBA APB PCIe CXL Python Perl Tcl Design-for-test Design-for-debug Physical Design Floor Planning Clock Tree Synthesis Power Grid Design

What you'll do

  • Author detailed micro-architecture specifications and implement Verilog RTL for major IP blocks.
  • Drive full ASIC development lifecycle from specification to post-silicon validation.
  • Develop timing constraints and resolve static timing analysis violations.
  • Integrate complex IP blocks into SOC environment ensuring proper connectivity and compliance with industry standards.
  • Implement design-for-test features and participate in RTL quality reviews.
  • Collaborate with physical design engineers on floor planning and clock tree synthesis.

What we're looking for

  • Proven track record with 2+ production ASIC tape-outs in senior roles.
  • Expert-level Verilog RTL coding skills and deep understanding of synthesizable constructs.
  • Hands-on experience across the full ASIC design flow from RTL to physical design.
  • Experience writing and debugging SDC timing constraints for complex designs.
  • Knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AHB/APB).
  • Strong ability to mentor junior engineers and lead design teams.

Related searches

More ASIC jobs ASIC jobs in Santa Clara All jobs at Amd

More like this

Similar roles

ASIC SoC Design Engineer

Amd

San Jose, CA 25 days ago
Verilog SystemVerilog Python Perl Makefile AMBA AXI APB UPF SDC SVA ASIC CAD tools Simulation Synthesis STA LINT LEC CDC RDC Power estimation
Hybrid
Save

Integration RTL Design Engineer

Amd

San Jose, CA 93 days ago
Verilog RTL PrimeTime Tempus SDC AMBA AXI AMBA AHB AMBA APB PCIe CXL Python Perl Tcl Design-for-Test Design-for-Debug Physical Design Floorplanning Clock Tree Synthesis Power Grid Design Formal Verification AI-assisted Design Tools EDA Technologies
Hybrid
Save

Senior ASIC Design Engineer, Clocks IP

Nvidia

Santa Clara, CA +1 20 days ago $136,000–$218,500
Verilog Python RTL Logic Synthesis CI/CD Sub-micron Silicon Issues Clocking Networks Clocks Controller Power Optimization DFT Silicon Debug Noise Analysis Cross-talk Analysis OCV Effects Scalable Designs
Hybrid
Save

Micro-architect/Logic Designer, Coherent Interconnect

Samsung Electronics

Remote (San Jose, CA) 17 days ago $151,000–$251,800
Verilog VHDL Perl Python STA DFT ECO AMBA5_CHI AMBA4_ACE AXI coherent_interconnect memory_controller cache_design mesh_topology ring_topology crossbar_topology RTL_design ASIC_design_flow logic_synthesis prototyping bring-up&_lab_debug
Remote
Save

Processor ASIC RTL Design Engineer

Qualcomm

San Diego, CA 51 days ago $127,200–$190,800
SystemVerilog RTL Verilog Linting CDC LEC CLP Processor integration Bus interface Cache Digital design Logic design
Save