Integration RTL Design Engineer

Amd

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$166,400–$249,600 / yr
Posted
169 days ago
Freshness
Confirmed live yesterday
Closes
Jun 18, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $185k
This role $208k
$134k most similar roles pay here $262k

This role pays more than 64% of similar roles. Most pay $152,968–$216,250 — the shaded band above. At the midpoint, this role pays about $208k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Integration RTL Design Engineer

Role Posting Log in to save

As an Integration RTL Design Engineer on the Silicon Design team, you will design and develop cutting-edge IPs for next-generation embedded products. You will own the complete RTL design lifecycle, from micro-architecture specification through production silicon, while managing complex IP designs to meet PPA targets. Your daily work involves authoring Verilog RTL, performing static timing analysis using PrimeTime or Tempus, and ensuring compliance with AMBA AXI/AHB/APB, PCIe, and CXL protocols. You will integrate blocks into a full-chip SOC environment, manage clock domain crossings, and collaborate with physical design teams on floorplanning and power grid design. To enhance productivity, you will develop automation scripts using Python, Perl, or Tcl. This role addresses the technical challenges of high-performance silicon integration, requiring expertise in low-power techniques, formal verification, and advanced EDA technologies for complex SoC environments.

Skills

Verilog RTL Design ASIC SoC STA SDC PrimeTime Tempus AMBA AXI AHB APB PCIe CXL Python Perl Tcl DFT Low-Power Design

What you'll do

  • Author detailed micro-architecture specifications and implement Verilog RTL for major IP blocks while meeting PPA targets.
  • Manage the full ASIC development lifecycle from initial concept through production silicon and post-silicon validation.
  • Develop, maintain, and resolve timing constraints using industry-standard tools to achieve successful timing closure.
  • Integrate complex IP blocks into SoC environments ensuring compliance with AMBA, PCIe, and CXL protocols.
  • Partner with verification teams to ensure functional coverage and implement design-for-test (DFT) features.
  • Collaborate with physical design engineers on floorplanning, placement constraints, and clock tree synthesis.
  • Develop Python, Perl, or Tcl scripts to automate repetitive tasks and improve design flow efficiency.
  • Mentor junior engineers and lead design teams to resolve complex technical challenges.

What we're looking for

  • Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
  • Proven track record with at least 2 production ASIC tape-outs in senior design roles.
  • Expert-level Verilog RTL coding skills and deep understanding of synthesizable RTL constructs.
  • Experience with the complete ASIC design flow from RTL through synthesis, STA, physical design, and tape-out.
  • Proficiency in writing and debugging SDC timing constraints and performing static timing analysis.
  • Knowledge of industry-standard protocols such as AMBA AXI/AHB/APB, PCIe, CXL, and ARM architecture.
  • Proficiency in scripting languages including Python, Perl, Tcl, or Shell to automate design tasks.
  • Experience mentoring junior engineers and leading design teams in cross-functional environments.

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