Integration RTL Design Engineer

Amd

Hybrid

Quick summary

Work type: Hybrid
Location: San Jose, CA
Posted: 93 days ago
Closes: Jun 18, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $180k

$127k most similar roles pay here $223k

This listing doesn't post a salary. Most similar roles pay $151,000–$208,900.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 56 open roles on FindRole.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Integration RTL Design Engineer

Role Posting Log in to save

As a Senior ASIC Design Engineer at AMD’s Silicon Design team, you will lead the design and development of cutting-edge IPs for next-generation embedded products, owning the RTL design lifecycle from micro-architecture specification to production silicon. Your daily tasks include Verilog RTL coding, timing closure, and collaboration with physical design teams to ensure successful tape-outs. You will drive projects through all phases of the ASIC development cycle, integrate complex IP blocks into SOC environments, and work closely with verification teams to enhance design quality. Essential skills include expertise in Verilog RTL coding, comprehensive knowledge of the full ASIC design flow, proficiency in scripting languages like Python and Perl, and experience with industry-standard protocols such as AMBA AXI/AHB/APB. This role demands a candidate with multiple production tape-outs under their belt and strong mentorship abilities to lead junior engineers effectively.

Skills

Verilog RTL PrimeTime Tempus SDC AMBA AXI AMBA AHB AMBA APB PCIe CXL Python Perl Tcl Design-for-Test Design-for-Debug Physical Design Floorplanning Clock Tree Synthesis Power Grid Design Formal Verification AI-assisted Design Tools EDA Technologies

What you'll do

Author detailed micro-architecture specifications and implement Verilog RTL for major IP blocks.
Drive design from concept through production silicon across all phases of the ASIC lifecycle.
Develop and maintain timing constraints to resolve timing violations and achieve closure.
Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity.
Partner with verification teams to ensure comprehensive functional coverage and DFT features.

What we're looking for

Proven track record with 2+ production ASIC tape-outs in senior design roles.
Expert-level Verilog RTL coding skills and deep understanding of synthesizable constructs.
Hands-on experience with the complete ASIC design flow from RTL to physical design.
Experience writing and debugging SDC timing constraints, including multi-cycle paths.
Knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AHB/APB).
Proficiency in scripting languages: Python, Perl, Tcl, or Shell scripting.
Experience mentoring junior engineers and leading design teams.

Similar roles

Principal Memory Controller RTL Design Engineer

Microsoft

9 days ago $142,800–$274,800

Verilog SystemVerilog Perl Tcl Python Reed-Solomon-Encoding CHI APB AMBA Synthesis STA CDC_checkers low_power_static_checkers linting_tools

Save

ASIC/SoC Design Engineer, RTL design for SoC IPs

Amd

Santa Clara, CA 128 days ago

Verilog RTL PrimeTime Tempus SDC AMBA AXI AMBA AHB AMBA APB PCIe CXL Python Perl Tcl Design-for-test Design-for-debug Physical Design Floor Planning Clock Tree Synthesis Power Grid Design

Hybrid

Save