ASIC Engineer, CAD

Cisco

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$155,000–$222,600 / yr
Employment
Full-time
Posted
44 days ago
Freshness
Confirmed live yesterday
Closes
Nov 6, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $198k
This role $189k
$141k $240k
below market most similar roles pay here above market

This role pays more than 51% of similar roles. Most pay $167,900–$227,300 — the blue band above. At the midpoint, this role pays about $189k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC Engineer, CAD

ASIC Engineer- CAD joins the Silicon One team to develop, maintain, and enhance DFT CAD infrastructure and automation. The role involves supporting DFT implementation flows such as Scan insertion, ATPG generation, and SPF generation while developing utilities and automation. Key responsibilities include debugging flow failures, creating regression frameworks and dashboards, and supporting large-scale regressions on compute farms using LSF or equivalent job schedulers. The candidate will utilize Python, Perl, Tcl, and Shell scripting alongside Verilog and SystemVerilog programming. Proficiency with industry-standard DFT/EDA tools and Synopsys Design Constraints is required. This position addresses technical challenges in creating hardware platforms for switching, routing, and wireless products, specifically focusing on improving flow robustness, runtime, and scalability within the silicon design and production lifecycle.

What you'll do

  • Develop, maintain, and enhance DFT CAD infrastructure and automation.
  • Support DFT implementation flows including Scan insertion, ATPG generation, and SPF generation.
  • Develop utilities and automation using Python, Perl, Tcl, and Shell scripting.
  • Debug DFT flow failures and resolve issues with design teams.
  • Create and maintain regression frameworks and dashboards.
  • Support large-scale regressions on compute farms using LSF or equivalent job schedulers.
  • Develop documentation, FAQs, and onboarding material for internal users.
  • Support releases, tool qualification, and regression signoff.

What we're looking for

  • Bachelor’s degree in Electrical or Computer Engineering with 5+ years of ASIC Design experience.
  • Master's degree in Electrical or Computer Engineering with 3+ years of experience.
  • PhD in Electrical or Computer Engineering with 0 years of experience.
  • Experience with Verilog/SystemVerilog programming.
  • Experience with interactive and waveform debugging.
  • Experience with industry-standard DFT/EDA tools and resolving flow and methodology issues.
  • Scripting experience in Python, Perl, TCL, or shell programming.
  • Experience with Synopsys Design Constraints (SDC) (preferred).

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