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Qualcomm

Quick summary

Work type: On-site
Location: San Diego, CA
Posted: 17 days ago
Closes: Nov 16, 2026
Nearby: 99+ roles within 25 mi

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Similar $191k

$133k most similar roles pay here $229k

This listing doesn't post a salary. Most similar roles pay $165,150–$216,250.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 270 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 196 roles with salary data.

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At a glance

TL;DR · Careers

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Join Qualcomm Technologies as a Senior Digital Power IP Verification Engineer on their cutting-edge team responsible for the entire verification lifecycle from concept to post-silicon support. In this role, you will plan comprehensive pre-silicon tests, develop testbenches using SystemVerilog-UVM, create coverage and assertion models, and perform formal verification. You’ll also learn and implement power-aware UPF verification flows and develop automation scripts to enhance efficiency. Ideal candidates have a Master’s degree in Computer Science or Electrical Engineering and at least 6 years of experience with ASIC design tools, digital RTL languages like SystemVerilog, UVM methodologies, and scripting languages such as Perl or Python. Familiarity with AMBA bus protocols and assertion-based formal verification is beneficial but not required.

Skills

SystemVerilog UVM SystemVerilog-UVM C++ C Perl Python VHDL Verilog AMBA_Bus_Protocol Formal_Verification Assertion_Based_Formal_Verification

What you'll do

Develop comprehensive pre-silicon test plans for digital power IP.
Create and maintain advanced verification methodologies using SystemVerilog-UVM.
Design coverage models to ensure thorough testing of digital power IPs.
Develop assertion models and perform formal verification on power IPs.
Implement automation scripts to enhance verification process efficiency.

What we're looking for

2+ years of ASIC design and verification tools experience
Bachelor's degree in Engineering, Science, or related field
Experience with SystemVerilog-UVM for testbench development
Skills in coverage, assertion model, and formal verification development
Proficiency in scripting/automation using Perl or Python

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