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ASIC Design Engineering Technical Leader

Cisco

San Jose, CA 2 days ago $183,800–$263,600
Actively hiring Posted this week Verified listing Above market
Verilog SystemVerilog RTL Timing_Closure Power_Optimization Clock_Gating ASIC_Development_Flows Simulation Synthesis Static_Timing_Analysis Python Perl TCL Shell Emulation Prototyping Formal_Verification_Pods
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ASIC Design Engineer Technical Lead

Cisco

Remote (San Jose, CA) 3 days ago $183,800–$263,600
Actively hiring Posted this week Verified listing Above market
Verilog SystemVerilog Python Perl TCL shell programming CDC Spyglass digital design principles microarchitecture concepts buffering scheduling architectures
Remote
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ASIC Design Verification Engineering Technical Leader

Cisco

Remote (San Jose, CA) 11 days ago $183,800–$263,600
Actively hiring Verified listing Above market
SystemVerilog UVM Linux C++ Python Perl Veloce Palladium Zebu HAPS CI/CD Networking Dashboard_management Emulation_platforms
Remote
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