Advanced Packaging Design Engineering Team Lead

Cisco

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$186,900–$267,700 / yr
Employment
Full-time
Posted
3 days ago
Freshness
Confirmed live yesterday
Closes
Feb 23, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $203k
This role $227k
$150k $280k
below market most similar roles pay here above market

This role pays more than 73% of similar roles. Most pay $173,432–$231,600 — the blue band above. At the midpoint, this role pays about $227k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 288 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 225 roles with salary data.

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At a glance

TL;DR · Advanced Packaging Design Engineering Team Lead

The Advanced Packaging Design Engineering Team Lead joins the Cisco Silicon One team to drive complex package design programs for high-performance Silicon ASICs. This role involves leading and mentoring engineers through the full development lifecycle from concept to tapeout, ensuring the delivery of scalable solutions for global networks. Key responsibilities include optimizing package pinouts, stack-ups, power distribution, and high-speed routing while collaborating with silicon floor planning, signal integrity, and power integrity teams. The position requires expertise in high-speed package design, power distribution networks, and industry-standard EDA tools for package layout. Candidates should possess experience with testing equipment like oscilloscopes and TDR/VNA analyzers, as well as scripting languages including Python, Perl, TCL, or shell programming to support advanced IC package design and heterogeneous system integration.

What you'll do

  • Lead complex package design programs from initial concept through implementation and tapeout.
  • Optimize package pinouts, stack-ups, power distribution, and high-speed routing for performance and reliability.
  • Collaborate with silicon floor planning, signal integrity, and power integrity teams to ensure system-level alignment.
  • Work with layout editors and implementation teams to deliver high-quality package layouts.
  • Serve as the technical and organizational lead for the San Jose package design team.
  • Mentor engineers and develop the team's package design capabilities and leadership.
  • Coordinate resources across designers, layout editors, and contractors to ensure efficient project execution.
  • Enhance package design methodologies and partner with vendors to improve product quality and efficiency.

What we're looking for

  • Must live within commuting distance of the San Jose, CA office and commute 4-5 days per week.
  • Bachelor’s degree in electrical engineering or a related field with 8+ years of relevant work experience.
  • Master’s degree in Electrical Engineering or a related field with 6+ years of relevant work experience.
  • Experience in high-speed package design, including signal integrity considerations and power distribution networks (PDN).
  • Experience with industry-standard EDA tools for package layout and design.
  • Experience with technical leadership in complex hardware or silicon development programs.
  • Experience in ASIC package design, including pinout optimization and high-speed routing (preferred).
  • Experience with testing and measurement equipment (oscilloscopes, TDR/VNA analyzers) or scripting languages like Python (preferred).

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