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Serdes Silicon Design and Micro-Architecture Engineer

Amd

San Jose, CA 6 days ago $232,000–$348,000
Actively hiring Confirmed live today Posted this week High trust Above market
Analog/Mixed-Signal Circuit Design Transceiver Micro-architecture CMOS PDK PHY Design CDR Clocking Circuits Pre-tapeout Verification Silicon Validation Firmware Loops Post-silicon Validation

Core RTL/Microarchitecture Power Lead

Amd

Santa Clara, CA 6 days ago $232,000–$348,000
Actively hiring Confirmed live today Posted this week High trust Above market
Microprocessor Architecture RTL Verilog System Verilog Low Power Design Logic Design PTPX Python Ruby Perl Shell Synthesis Place and Route Timing Closure Physical Design AI LLMs Performance Simulators

CPU Performance, Principal Microarchitecture Exploration Engineer

Arm Holdings

Austin, TX +1 8 days ago $249,900–$338,100
Actively hiring Confirmed live yesterday High trust Above market
CPU Microarchitecture Performance Modeling Cycle-accurate Simulators C++ Python Workload Analysis Performance Profiling power, and area trade-offs Software Engineering Practices
10+ yrs exp Hybrid

SerDes Silicon Design and Micro-Architecture Engineer

Amd

San Jose, CA 12 days ago $188,160–$282,240
Actively hiring Confirmed live today High trust Above market
Analog/Mixed-Signal Circuit Design Transceiver Micro-architecture CMOS PDK PHY Design CDR Clocking Circuits Pre-tapeout Verification Silicon Validation Post-silicon Validation Firmware Loops

CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm

Santa Clara, CA +1 25 days ago $175,600–$263,400
Actively hiring Confirmed live today Trusted Competitive pay
RISC-V RTL Design Verilog VHDL Microarchitecture Python Perl Logic Design Functional Verification Waveform Debugging Simulators Out-of-Order Execution
4+ yrs exp

CPU Microarchitecture & Cache RTL Design Engineer

Amd

Fort Collins, CO 34 days ago $144,800–$217,200
Actively hiring Confirmed live yesterday High trust Below market
VLSI RTL Design Verilog HDL Cache Architecture CPU Coherency NoC SoC Scripting Microarchitecture Timing Closure Design for Test Physical Design Routing Fabric

Principal Competitive CPU Microarchitecture & Platform Performance Engineer

Amd

Austin, TX 39 days ago $200,000–$300,000
Actively hiring Confirmed live yesterday High trust Above market
CPU Microarchitecture Performance Modeling System Architecture Hardware Performance Counters NUMA TLB PCIe CXL HBM DDR data-analysis Scripting Virtualization HPC Power Modeling ISA Telemetry Bottleneck Analysis

Chief Competitive Performance & Microarchitecture Analysis

Amd

Austin, TX 45 days ago $200,000–$300,000
Actively hiring Confirmed live today High trust Competitive pay
x86 Arm CPU Architecture Performance Modeling Benchmarking NUMA TLB I/O Statistical Interpretation Silicon Performance Counters Platform Telemetry Experimental Design

Senior Lead Software Engineer, Full Stack

Capital One Financial

Richmond, VA +1 78 days ago
Actively hiring Confirmed live yesterday Low trust
Java Python AWS Kafka Jenkins TypeScript Go SQL Docker Kubernetes Microservices JavaScript HTML/CSS NoSQL RDBMS Azure GCP Agile Claude Code
6+ yrs exp