Browse tech roles

Cadence_APD SiP_tool_suite Constraint_Manager Virtuoso Calibre Valor HDI_designs PCB_layout Wire_bond_packages Flip_chip_packages +5 more Show less

Cadence_APD SiP_tool_suite Constraint_Manager Virtuoso Calibre Valor PCB_layout HDI_design High_speed_design Signal_integrity_practices Python C++ Perl Tcl Git CI/CD +11 more Show less

Altium Designer Allegro USB PCIe Ethernet SERDES DDR memory RF board design FPGA fanout +4 more Show less

Cadence_Innovus CAD_Automation PCell_creation

SiemensMentorXpedition CadenceAllegroPCBdesignsoftware ValorCAM350tools RF Analog High-speeddigitalcircuits DDR5 HDMI PCIe SATA MIPI USB23x GigE LPDDRbreakouts complexstackups EMImitigationtechniques IDFEMNfileexchange +12 more Show less

Siemens_Xpedition Cadence_Allegro_ECAD_Tools Sequential_Lam_Structures HDI FPGA SERDES DDR_memory_structures USB PCIe Ethernet High-speed_digital_interfaces Controlled_impedance_routing Signal_and_power_integrity_rules Air-Gapped_Network_Environments +9 more Show less

Siemens_Xpedition Cadence_Allegro_ECAD_Tools Sequential_Lam_Structures HDI FPGA SERDES DDR_memory USB PCIe Ethernet High_speed_digital_interfaces Controlled_impedance_routing Signal_and_power_integrity_rules Air-Gapped_Network_Environments +9 more Show less

Linux

Linux IC layout design Analog layout skills

Linux IC layout design Analog layout skills

Linux IC layout design

Linux IC layout design

Linux IC layout design

Cadence_Innovus CAD_Automation PCell_creation

Cadence_Innovus CAD_Automation PCell_Creation Verilog MSEE PhD +1 more Show less

Cadence_Innovus CAD_Automation PCell_creation Verilog MSEE PhD +1 more Show less

Cadence_Innovus CAD_Automation PCell_creation Verilog MSEE PhD +1 more Show less

Cadence_Innovus CAD_Automation PCell_creation

Cadence_Innovus CAD_Automation PCell_Creation

Cadence_Innovus CAD_Automation PCell_creation VLSI_Design Analog_Design Layout_Engineering Verilog SPICE_Simulation Python Git Linux TCL SVPHILE Calibre SkyWater_PDK OpenROAD +11 more Show less