Senior Package Layout Engineer - Hardware

Nvidia

Remote

Quick summary

Work type
Remote
Location
Santa Clara, CA
Salary
$136,000–$212,750 / yr
Posted
17 days ago

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $189k
This role $174k
$124k most similar roles pay here $246k

This role pays less than 62% of similar roles. Most pay $155,013–$222,000 — the shaded band above. At the midpoint, this role pays about $174k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior Package Layout Engineer - Hardware

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NVIDIA seeks a Senior Package Layout Engineer to join its innovative team, focusing on the design and development of advanced IC substrates for cutting-edge products. This role involves collaborating closely with technical leads and various design teams to implement high-speed/density ASIC packages, perform substrate breakout patterns, optimize package pinout, and conduct feasibility studies to ensure optimal size, cost, and performance. Key responsibilities include using Cadence APD or SiP tool suite for routing, placement, stack-up, reference plane, and power distribution, as well as developing methodologies to enhance layout productivity. Ideal candidates hold a B.S. in Electrical Engineering with 5+ years of experience in PCB Layout, preferably including HDI designs, substrate layout of wire bond and flip chip packages, and proficiency in Cadence APD or SiP tools.

Skills

Cadence_APD SiP_tool_suite Constraint_Manager Virtuoso Calibre Valor HDI_design PCB_layout Wire_bond_packages Flip_chip_packages

What you'll do

  • Perform substrate breakout patterns for ASIC packages.
  • Optimize package pinout considering system-level trade-offs.
  • Conduct package routing, placement, stack-up, reference plane, and power distribution.
  • Propose layout design trade-offs to the Technical Package Lead.
  • Develop symbols and CAD library databases using Cadence APD tools.
  • Conduct feasibility studies to evaluate package design goals for size, cost, and performance.

What we're looking for

  • Hold a B.S. in Electrical Engineering or equivalent experience.
  • 5+ years of PCB layout experience for graphics cards, motherboards, etc.
  • Proven expertise in substrate layout for wire bond and flip chip packages.
  • Proficient with Cadence APD or SiP and PCB layout tools like Constraint Manager.
  • Strong understanding of high-speed design signal integrity practices.
  • Experience with Virtuoso and Calibre is beneficial.

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